收發轉換器 的英文怎麼說

中文拼音 [shōufāzhuǎnhuànqì]
收發轉換器 英文
anti t-r switch
  • 收 : Ⅰ動詞1 （把攤開的或分散的事物聚集、合攏） put away; take in 2 （收取） collect 3 （收割） harvest...
  • 發 : 名詞（頭發） hair
  • 轉 : 轉構詞成分。
  • 換 : 動詞1. （給人東西同時從他那裡取得別的東西） exchange; barter; trade 2. （變換; 更換） change 3. （兌換） exchange; cash
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 收發 : 1 （收進和發出公文） receive and dispatch2 （擔任收發工作的人） dispatcher3 [電學] transmit recei...
  • 轉換器 : -ad
  • 轉換 : change; transform; convert; switch
  1. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬信號調理模塊對輸入的信號進行調理，以達到系統和模數轉換器（ adc ）采樣的要求; dsp作為系統的核心部件，外擴了adc 、以太網控制器、 rs - 485總線收發器、 can總線收發器和時鐘晶元， dsp對實時數據進行處理，當報警發生時將實時數據通過以太網上傳給上位機。
  2. To utilize the advantages of dsp chips, the system should be computing sources economical. according to digital signal processing theory, the poly - phase fir can help reduce the workloads of the ddc / duc. therefore, adding the complex carrier mixers, the channelization system ( a method of using a single wideband facility to transmit many relatively narrow - bandwidth signals. by subdividing the frequency spectrum used in the wideband channel ) can be formed utilizing the characters of fft

    為了使開發出的軟體可以適用於高速dsp器件開發，節省系統資源，課題首先從數字信號處理的理論進行分析，得出可以利用抽樣率轉換的數字濾波器的特點，即多相濾波實現數字上下變頻計算負擔的減小，之後進一步將多相濾波器與頻譜搬移部分結合，通過公式的推導，得出可利用快速傅立葉變換的特點實現多路信號的通道化發射和接收的處理模型。
  3. Through analysising the characteristics of the power system with floating neutral point deeply, the paper puts forward a new plan of single - phase to ground fault line selection on the base of s ' s signal injecton method and gives the hardware and software design. in this design, the high speed sampling and data processing is carried out through using dsp processor ; the large electrice current is drived through the application of a high - performance audio power amplifier and transformer ; the communication between host computer and detectors is realized through rs485 bus technology ; the difference multilevel frequency - selected amplifier is designed and the feeble signal of space is sampled on the base of the theory of magnetic induction ; the interface between dsp and exterior chip and rs485 interface logical is designed through using fpga ; the using of lcd module and keyboard interfacing chip makes the interface between human and machine ; the programme of host computer and detectors is designed through using blocking design method

    在本設計中，採用高速的dsp處理器，實現了對故障特徵信息的高速採集與處理;採用大功率的功放晶元與變壓器配合的方法，實現了大電流信號的驅動輸出;採用485總線技術，組建了裝置主機與多探測器之間的主從式通訊網路，實現了多干擾條件下裝置主機與多探測器的可靠通訊;設計了差分式多級選頻放大電路，採用磁感應的方法實現了對空間微弱信號的接收;利用fpga技術，實現了控制器與多外設的介面及數字信號的串並轉換;採用了先進的lcd液晶顯示模塊及鍵盤介面晶元，設計了人機信息交互的介面;採用了模塊化的軟體設計方法，開發了裝置主機及探測器的軟體程序。
  4. In the transmiting port, optical encoder turns data bits into spread spectrum sequences, then, optical decoder retverts it to data bits with the theory of correlation decoding in the receiving port

    在發送端光編碼器將數據比特轉換成擴頻序列，在接收端光解碼器利用相關解碼原理將擴頻序列恢復為數據比特。
  5. This thesis focuses on the ingress process module of ctu, which translates c - 5 dcp format to rainier 4gs3. the specification analysis, architecture and logic design, functional simulation testbench design, synthesis report and testing result are discussed in this thesis. the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module, which includes receive control fsm, send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed

    本論文的主要研究工作包括：通信協議轉換邏輯的功能分析和設計需求；通信協議轉換邏輯上行方向的系統分析及體系結構設計，包括上行接收狀態機、發送狀態機、信元內位元組位置調整機制等的設計；通信協議轉換邏輯上行方向的線速設計，主要是上行接收的線速設計，要使用流水設計技術；提出了高速實現roundrobin調度策略的實現方法，並設計實現了桶式移位器和優先級編碼電路；應用bfm模擬模型設計了上行處理各模塊的模擬testbench ，完成了各級模塊的模塊模擬和系統集成模擬。
  6. The design of hardware module includes a / d converter, ddc ( digital down converter ), duc ( digital up converter ) and dsp. the design and application of ad6640 and ad6624 are fully discussed in this part. the design of software module includes the parameter design for ddc filter and the base - band signal processing of dsp

    收發信機硬體設計主要包括： a d 、 d a轉換器、數字下變頻器（ ddc ） 、數字上變頻器（ duc ）以及dsp ，論文詳盡介紹了a d器件ad6640 、 ddc器件ad6624和dsp器件tms320c5410的設計和應用；收信機軟體設計主要包括： ddc濾波器參數設計和dsp的基帶信號處理，給出了dqpsk調制、解調演算法的dsp實現。
  7. During the design of vxi - bus serial controller module, the functions of vxi - bus including time - sequence for vxi interface, resource management, interrupt process, bus arbitration, are accomplished. to advance the performance and stability, the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence, the uart, the parameterized baud generator and “ pipeling frame ”. the handle type of data transfer bus for vxi - bus is researched thoroughly, and the format of serial data transfer is designed

    在vxi總線串列控制器設計中，實現了vxi總線控制器的基本功能，包括vxi總線介面時序、總線仲裁、超時處理等;同時利用先進的fpga技術實現了串列總線時序向vxi總線時序的轉換、通用異步收發器（ uart ） 、參數化波特率發生器、流水線結構等功能模塊;在設計中還深入研究了vxi總線數據傳輸的各種操作類型，制定了串列數據傳輸的編碼格式。
  8. Travel time is the key point of system, its measure quality decides the survey precision of the stress. time to digital convertor ( tdc ) was applied to accomplish the precision time interval measurement. at the same time, one transmitter - two receivers probe arrangement and zero - crossing detecting method were also applied to reduce the errors in measurement

    傳播聲時是整個測量系統中的關鍵量，其測量水平決定應力的測量精度，對此本文採用時間-數字轉換器（ timetodigitalconvertor ， tdc ）完成高精度時間間隔測量，在實現過程中又分別採用「單端發射-雙端接收」的探頭布局模式和「過零檢測」手段來降低系統檢測誤差。
  9. This card largely depends on three integrate chips to fulfill its function : 1 ) nic control main chip, corresponding the mac sublayer of ethernet, to realize csma / cd media access protocol, manage the sending and receiving buffers integrated on the chip and provide motherboard pci interface. 2 ) serdes ( serializing and deserializing ) chip, corresponding pcs and pma sublayers in ethernet, mainly to complete 8b / 10b coding and convert 10 bits parallel data to serial data, and convert them again at the receiving end. 3 ) fibre transceiver unit, completing light - electrical conversion of seri

    該網卡主要由3塊集成的晶元完成其功能，分別是i ）網路控制主晶元，對應于以太網的mac子層，主要完成csmaicd介質訪問協議，管理片上集成的發送和接收緩沖區，並提供和主板p0總線的介面： b ） s rd s （串列解串列化器）晶元，對應于以太同的pcs和pma子層，主要完成sb lob編碼並將10位并行的數據轉換為串列數據，在接收端完成相反的功能：涌）光纖收發器，完成串列數據的光電轉換功能。
  10. Modem - an abbreviated term for " modulator - demodulator. " a modem converts digital signals into analog signals ( and vice versa ), enabling computers to send and receive data over the telephone networks

    數據機- -是「調制器和解調器」的縮寫。數據機可將數字信號轉換成模擬信號（反之亦然） ，能使電腦在電話網上發送和接收數據。
  11. Hence, the requirements of the servo control card are getting much sophisticated. in this thesis, the research work and implementation details of a 6 axes servo control card are discussed. this card is based on the ti company ? dsp chip tms320f240 and has realized the following functions : a ) signal encoder, b ) position limit, c ) dual ram communication with cpu, d ) coordinated control e ) dia conversion

    該卡以ti公司的16位定點數字信號處理器tms320f240為核心晶元，實現6路編碼器信號輸入處理，軸限位中斷處理，通過雙埠ram與pc進行通訊，接收pc發送過來的控制指令和數據，完成插補運算、聯動運算等控制，通過d / a轉換電路，將結果轉化為模擬電壓送伺服放大器驅動電機。
  12. We put forward a scheme that multisensor data fusion - surface fitting and curve - fitting was applied in this system according to the temperature drift and nonlinear of sensor. communication between personal computer and measurement system of sensor was realized by means of transceiver with the type of max232, which could finish the data conversion, data processing and printing task, with the result that the measurement system was further improved

    針對傳感器測量的溫度漂移和非線性等問題，提出了利用多傳感器信息融合技術?曲面擬合法和曲線擬合法來加以解決，並通過max232收發器實現pc機與傳感器測量系統之間的通信，完成數據轉換、數據處理和列印等功能，使測量系統更加完善。
  13. Advanced fpga technology is introduced to improve the integration of digital circuits, and all digital circuits in the original module are integrated in the fpga chips, which could not only reduce the cost, but also improve the reliability and measurement precision of the circuits. high speed digital signal processor ( dsp ) is selected as the coprocessor instead of scm ; it can receive all kinds of commands sent from vxi, analyze and execute the commands, harmonize each section of the module and process the data. higher - conversion - speed comparator chip is adopted to convert the input signals being measured into square waveform signals which could be identified by fpga chip ; it can expand the measurement range of frequency dramatically

    本文在原有vxi總線四通道計數器模塊的設計基礎上，通過對原模塊缺陷的分析，採用一些新的技術和新的電子器件來重新設計該計數器模塊:採用最新的fpga技術來提高數字電路的集成度，將原模塊中的所有數字電路全部集成在fpga晶元中，這樣不僅能節約成本，還能提高電路的可靠性和測量精度;採用高速的數字信號處理器（ dsp ）取代原有的單片機作為協處理器，來接收vxi發來的各種命令，分析命令、執行命令、協調模塊各部分的工作以及對數據的處理;採用轉換速率更高的比較器晶元將輸入的被測信號轉換為fpga晶元能夠識別的方波信號，能極大提高測量頻率的范圍;採用d / a轉換晶元和隔離運算放大器得到隔離通道所需的比較電平，該比較電平值能夠根據實際需求進行設置，能增強模塊的使用靈活性。
  14. A network switch system that includes a plurality of first - level switches operating in a slave mode, the first - level switches providing a plurality of local ports for receiving and sending network packets, and a plurality of second - level switches operating in one of brain mode or master mode, wherein, the first - level switches includes a plurality of upward ports connecting to the second - level switches, each of the first - level switches and the second - level switches having a forwarding database, wherein the first - level switches sends the refresh packets to the second - level switches for synchronizing the forwarding databases of the second - level switches, wherein the second - level switches providing packet communications among the first - level switch operating in the brain mode providing refresh packets to the first - level switches for synchronizing the forwarding databases of the first - level switches

    一種網路交換系統，包括：復數個操作在從架構模式的第一階交換器，此第一階交換器提供復數個在地埠以收送網路封包，和復數個操作在中樞架構模式或主架構模式下的第二階交換器，其中，第一階交換器包括復數個上行埠連接到第二階交換器，每一個第一階和第二階交換器內有一轉送資料庫，其中，第一階交換器發送更新封包到第二階交換器以同步位於第二階交換器內的轉送資斗庫，其中，第二階交換器提供第一階交換器彼此間的封包通訊，且其中，操作在中樞架構模式下的第二階交換器可發送更新封包到第一階交換器以同步位於第一階交換器內的轉送資料庫。
  15. The c8051f005 micro - processor made by cygnal company is the core of the lead plane, which connects with half - duplax differential transceiver max3471, sigma - delta ad7705. the pressure, altitude and temperature can all be collected and calculate out accurately

    主機以cygnal公司的c8051f005單片機為核心，外接串口通信收發器max3471 、 a / d模數轉換器ad7705 ，可以實現壓力、高度、溫度數據的採集和較為準確的輸出，同時還具有低電壓報警等輔助功能。
  16. Tofind a beam - type shelves and determine its position ， any radar station has to basically consist of a transmitter ， a receiver ， an antenna ， an bed set ， a display and a timer

    為了要發現目標和確定其位置，任何雷達站基本上都必須包括發射機、接收機、天線、天線轉換開關、顯示器和定時裝置。
  17. In the system, the rotate speed sensor and torque sensor are fixed between the engine power output shaft of yanmar combine harvester and the power input shaft of working device. the signals of torque and rotate speed are preprocessed such as v / f, amplified. and the power is computed

    該系統在洋馬聯合收割機的發動機動力輸出與工作裝置的動力輸入軸之間安裝了轉速和扭矩傳感器，對轉速和扭矩傳感器的輸出信號進行v f轉換、放大等預處理，並計算出功率值。
  18. Specifically, the development of high speed a / d converter, dds technology, as well as the prevalence high speed dsp, fpga have provided a solid hardware function for the radar receiver

    特別是高速多位（ 100mhz ， 12bit以上） a / d轉換器和dds技術的發展以及高速數字信號處理晶元（ dsp ）和fpga的普遍使用，為雷達接收機提供了良好的硬體基礎。
  19. In the description of circuit design, the emphasis is paid the following hardware modules : ad / da inverter, dsp module, external program / data memory, cpld control logic, serial communication module, power module, and so on. problems and the corresponding solutions found in the design and debug stage are discussed, too. finally, the low - level software driver design is presented in detail, including system booting, initialization of dsp registers, cpld logic and timing control, drivers for asynchronous communication fifo, and drivers for ad converter

    在電路模塊分析中，重點介紹了語音的輸入放大和輸出緩沖部分、 ad da轉換、 dsp語音壓縮解壓、外部程序數據存儲器、 cpld邏輯控制、串列收發組件、電源供電以及dsp的jtag介面等等，並且給出了在硬體電路設計和調試過程中的問題與解決辦法。
  20. Lastly, the working theory of encoder, decoder and optical transceiver of the optical wireless lan are analyzed. the experiments about the system are done in the paper and basically realize the wireless optical lan

    最後，本論文具體分析了光無線局域網系統各個組成部分，主要是光電轉換器和光收發器的工作原理，並進行了實驗製作。
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