放線儲存器 的英文怎麼說

中文拼音 [fàngxiànchǔcúnqì]
放線儲存器 英文
pay-off accumulator
  • 放 : releaseset freelet go
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 儲 : Ⅰ動詞（儲藏; 存放） store up; save; keep [have] in reserve Ⅱ名詞1. （繼承人） heir 2. （姓氏） a surname
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. Main technic of giss webgiso thus function modules architecture and network topological structure are confirmed webgis system implements the basic function of electronical map, such as map zoonu pan, and the abundant query of geograph and database by using maplnfo mapxtreme for java as map server and jsp., java technico this system also can implement the routing of linesx analysing of buffer and so on0 this paper advances storage model of roads and pipelines topology data, efficiently solves the maintenace problem of network topology data of webgis and implements the shortest path algorathm based on webgis by improving it0 the system has better opening by suppling database interface of map ? the system has perfect on - line help and user forum and favorable interfaces and implementation of this system makes fundament for the further research of webgiso

    本系統利用mapinfomapxtremeforjava作為地圖服務器，採用jsp和java技術，實現了基於webgis的電子地圖的縮放、漫遊等基本功能，並具有豐富的圖文定位查詢功能；實現線路路由、緩沖區分析等輔助決策功能；構建了道路管線網路拓撲數據的存儲模型，有效地解決了基於webgis的網路拓撲數據的維護問題；對dijkstra演算法進行了一些改進，實現了基於webgis的最短路徑演算法；本系統提供了電子地圖數據庫介面，使本系統具有很好的開放性和通用性； webgis系統軟體具有完善的在線幫助和用戶交流論壇，人機界面友好。
  2. In order to improve the performance of the sram, array partition, divided word line structure and cmos positive feedback sense amplifier are adopted

    設計中採用了存儲陣列劃分、分級字線以及cmos正反饋差分讀出放大器等先進技術，讀寫速度可達到20ns 。
  3. On top of its conventional activities of signal magnification, reshaping, filtering, sampling, a / d transformation and scale switching, the intelligent sensor system can perform kinds of advanced operations such as on - line storage of parameters, real - time data processing, self - diagnosing of the system and so on. because of its communication interface with pcs, it serves as intelligent plug & play network sensor

    它除了能完成對傳感敏感器件的信號進行放大、整形、濾波、采樣、 a d變換及標度變換外，還可實現參數在線存儲、數據實時處理、系統自我診斷等功能，並可以通過其通訊介面與溫室現場總線相接，組成即插即拔的智能網路傳感節點。
  4. In mainly contains photoelectric converting and pre - amplifying circuits, lcd and keyset interface circuits and data storing circuits based on i2c bus

    主要包括光電轉換和信號前置放大電路、液晶屏和鍵盤介面電路和基於i ~ 2c總線的數據存儲器電路。
  5. This master degree thesis, based on the observing of developing actuality of on - site electrical apparatus monitoring technology, aims at overcoming the problems existing in former on - site monitoring system, such as unable to realize multiple channels sampling and hold, unable to carry out multiple channel programmable magnification, unable to monitor frequency, low pick up bits, external rom low speed data saving, inefficient data query method, inflexible debugging and installation, low precision etc. by introducing eda ( electrical design automation ) technology, we put forward a creative circuit design scheme, which can considerable updated the on - site monitor system

    本文根據電氣設備絕緣在線監測技術的發展現狀，針對以往在線監測數據採集系統存在的集成度低，不能實現多通路并行采樣，不能實現多通道同時程式控制放大，不能進行同步頻率監測，采樣位數較低，採用外部存儲器方式，對數據進行查詢的訪問方式，安裝調試不靈活等缺點，提出了應用現代微電子技術電子設計自動化（ eda ）技術實現對在線監測數據採集系統的改進。
  6. The floating - point a / d conversion scheme was employed to increase the system ' s dynamic range. complex programmable logic device ( cpld ) was also used to perform the system ' s function such as data sampling trigger control and data storage control, etc. aduc812, a new type of microprocessor with full a / d converter, was utilized to fulfill the a / d conversion

    在數據採集電路設計中，採用了浮點放大技術來提高系統的動態范圍；通過引入可編程邏輯器件來實現觸發控制、存儲控制；采樣過程中應用了時序重疊技術，從而實現了數據採集系統的流水線作業方式。
  7. Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology

    然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
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