數字時鐘 的英文怎麼說

中文拼音 [shǔzìshízhōng]
數字時鐘 英文
digital clock
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 數字 : 1. （表示數目的文字; 表示數目的符號） figure; digit; numeral; character; numeric character 2. （數量） quantity; amount
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. Lemaire then took just over a minute to identify two quadrillion, 397 trillion, 207 billion, 667 million, 966 thousand, 701 as the 13th root

    而勒麥爾只用了一分多鐘的時間就算出了這一長串數字的13次方根，答案是2397207667966701 。
  2. Automatic test pattern generation for multi - clock digital system based on s amp; amp; cct

    基於安全充分捕獲技術的多時鐘數字系統測試矢量生成
  3. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  4. Thirdly, the paper discusses the driver of the peripheral equipment, how to port the uc / os - n and uclinux, h. 323 protocol and the application of the system in the digital speech classroom. also some software and hardware measure are adopted to enhance the system stability. at last, the shortcoming and the something to be improved are given. dsp can be used to realize real - time speech coding algorithm, and after porting ( ac / os - n, arm can manage the keyboard, the lcd and the ethernet peripheral etc. then the embedded network system with specific purpose can be used in others fields, such as pda, set of top, web tv, ect

    在實際設計實現中，為提高系統軟、硬體整體穩定性和可靠性，使用了以下幾種方法： （ 1 ）低電壓復位、抗電源抖動能力、增加時鐘監測電路、抗電磁干擾能力、散熱等技術； （ 2 ）多層pcb設計，線路板結構緊湊，電源部分採用數字5v 、 3 . 3v 、 3v 、 1 . 8v和模擬5v多電源供電； （ 3 ）選用表面貼和bga封裝的器件； （ 4 ）按照軟體工程的要求進行系統分析，規劃系統框圖、流程分析、模塊劃分，減小了不同模塊的相關性，從而最大限度避免了錯誤的發生。
  5. Press d key and ? key to adjust the number of date and time ; press set key, and enter the next adjust process ; press mode key to quit the operation and return to “ adjust clock ? ”

    按d鍵和?鍵加減日期和時間的數字；按set鍵進入下一項目的調整；按mode鍵放棄調整，回到「調整時鐘？ 」
  6. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法，重點介紹了視頻信號數字化技術、抗混疊濾波器、箝位、增益控制、鎖相技術、同步時鐘產生、電視信號亮色分離、彩色解碼等技術，這些關鍵技術為視頻信號的數字化處理提供了重要的基礎。
  7. Make the minimum of p or simulated figures show a big bell, but still audible timekeeping, as london s " stupid bell, " the same. main functions are : - open lid can

    同時能使小p顯示一個大的數字或模擬鐘，而且還能發聲報時，就像倫敦的「大笨鐘」一樣。
  8. In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail

    文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案，並對其中主要功能模塊和關鍵演算法作出了詳細說明，包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。
  9. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  10. To contrast with the real clock and find the reason which cause the error and give the arithmetic which can minimize error, then lets the clock meet the need of production

    對比實際的時鐘，查找出誤差的來源，並作出調整誤差的方法，使得誤差盡可能地小，使得系統可以達到實際數字鐘的允許誤差范圍內。
  11. The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation

    再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。
  12. One of the most promising new technologies to help achieve that goal is a new breed of low - powered microprocessors that can vary the speeds at which they operate

    在執行復雜的計算任務，如連續處理大批的數字數據時，這種處理器以極高的速度，即"時鐘脈沖速度"運行。但是在執行要求較低的任務，如運行一個文字處理器或放音樂時，該晶元能減速。
  13. Of course the sampling clock is itself a digital signal

    時鐘本身也是數字信號，也會干擾模擬電路。
  14. This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution

    主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。
  15. Spb time is the one that would support the replacement of the skin pocket pc clock tool software analog and digital clock protocol, the long - time, timer, hutchison and stopwatch functions when combined

    2 . 85 mb spb time是一款應可以支持更換皮膚的pocket pc時鐘工具軟體，模擬和數字時鐘制式，多時區時間顯示，定時器，記時和秒錶功能相結合
  16. Digital clock management system and its application

    數字時鐘管理系統及其應用
  17. Varification regulation of standard digital clock

    標準數字時鐘檢定規程
  18. Digital clock timer segment timer

    數字時鐘定時器分段定時器
  19. The clock module provides the clock of the system. the clock module is based on digital colck manager of xilinx

    時鐘模塊通過數字時鐘管理器（ dcm ）為整個系統提供所需的時鐘。
  20. Lsi chips are medium to large size memory chips, 8 bit microprocessors, digital clocks or calculators

    大規模集成電路晶元是中等到大規模的記憶晶元，用於8位處理器、數字時鐘和計算器。
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