數字編譯碼器 的英文怎麼說

中文拼音 [shǔzìbiānyìmǎqì]
數字編譯碼器 英文
digital codec
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 數字 : 1. （表示數目的文字; 表示數目的符號） figure; digit; numeral; character; numeric character 2. （數量） quantity; amount
  • 編譯 : [計算機] compile; translate and edit編譯程序 compiler; compile programme; compiling routine; 編譯...
  1. The contents adds the to code the system ". the colloquy dvd sees the arithmetic figure to add the project. only the that the dvd that css admit to broadcast the to can just break password see data

    「內容加密編碼系統」 。正式的dvd視頻數字加密方案。僅css許可的dvd播放器才可以破譯視頻數據的密碼。
  2. Enhanced variable rate codec speech service option 3 for wideband spread spectrum digital systems

    寬帶頻譜擴展數字系統用增強的可變率編譯碼器語音服務選擇3
  3. Evrc 3 software distribution for tia - 127 - a - enhanced variable rate codec speech service option 3 for wideband spread spectrum digital systems

    Tia - 127 - a的軟體配置.寬帶頻譜擴展數字系統用增強的可變率編譯碼器
  4. The whole paper had been divided into four parts : the first part introduces the general situation of digital trunking system and its channel encoding, the recent development of viterbi decoding ; the second part studies the error control scheme, and the convolution decoding depth which is most fit to digital trunking system ; the third part introduces several low power viterbi decoder and its principle ; the last part proposes a united - decision estimating viterbi decoding algorithm

    本文共分為四部分，第一部分介紹了數字集群及其通道編碼的總體情況， viterbi譯碼的發展現狀。第二部分給出了數字集群系統中話音通道差錯控制總體方案，並研究了適合數字集群系統的卷積碼的解碼深度。第三部分簡單介紹了各種低功率viterbi譯碼器及原理。
  5. Both are used to separate the responsibility for rendering pages from the model and controller. both accept objects passed into them as an input argument, both allow inserting string values within code " expressions ", and allow direct use of java code to perform loops, declare variable, or perform logical flows " scriptlets ". both are good ways of representing the structure of a generated object web page, java class, or file while supporting customization of the details

    Jet與jsp非常類似：二者使用相同的語法，實際上在後臺都被編譯成java程序；二者都用來將呈現頁面與模型和控制器分離開來；二者都可以接受輸入的對象作為參數，都可以在代碼中插入字元串值（表達式） ，可以直接使用java代碼執行循環、聲明變量或執行邏輯流程式控制制（腳本） ；二者都可以很好地表示所生成對象的結構， （ web頁面、 java類或文件） ，而且可以支持用戶的詳細定製。
  6. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  7. This paper achieves expected digital filters program through algorithms descriptions, analyzing and realization, simulation, comparing on error and speed. this paper achieves expected digital interpolations program through algorithms descriptions, analyzing and realization, simulation, comparing on error and speed

    本文應用matlab信號處理工具箱，通過對數字濾波器演算法的描述、演算法分析、實驗模擬、誤差比較，及性能比較，最終獲得滿足要求的數字濾波程序，並編譯成c + +源代碼文件配合主程序調用，完成了系統聯調。
  8. After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance

    經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。
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