數據流水線 的英文怎麼說

中文拼音 [shǔjùliúshuǐxiàn]
數據流水線 英文
data pipeline
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 據 : 據Ⅰ動詞1 （占據） occupy; seize 2 （憑借; 依靠） rely on; depend on Ⅱ介詞（按照; 依據） according...
  • 流 : Ⅰ動1 （液體移動; 流動） flow 2 （移動不定） drift; move; wander 3 （流傳; 傳播） spread 4 （向壞...
  • 水 : 名詞1 （由兩個氫原子和一個氧原子結合而成的液體） water 2 （河流） river 3 （指江、河、湖、海、洋...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 數據 : data; record; information
  • 流水 : 1 （流動的水） running water; stream2 （舊時指商店的銷貨額） turnover （in business）流水搬運作用...
  1. The hardware has two input channels of high - speed analog signal, with the signal amplitude of 0 - 5v, the conversion precision of 12bits, and the maximum sampling rate of 400ksps. this system includes 4 dsps ( adsp 2181 ), which can be arranged as a pipe line processing array. many algorithms can be realized in this system

    系統硬體有兩路模擬數據採集通道，模擬信號輸入范圍為0 ? 5v ，轉換精度為12位，最高采樣率400ksps ；系統包含4片dsp （ adsp2181 ）構成的流水線型的處理陣列，可用於實現各種演算法；系統的控制邏輯由fpga完成。
  2. By classifying the original spatial data products in our market, and by referencing the design pattern of pipelining mode in industry, i brought out a universal model for producing spatial datasets, and also discussed the main content of this model

    因此，筆者在對目前市場上的空間源數據產品進行了分類后，以工業流水線生產模式的設計思路為藍本，提出了一個空間數據集生產流程的通用模型，並對該模型進行了論述。
  3. There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way

    Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。
  4. Abstract : a technical solution for the multi - channel random data stream by tsr receiving programming is presented. details about resident interrupt receiving, data buffer setup, data segment address keeping, buffer read / write operation and program resident / unresident are described ， and information process programming with advanced language is discussed. the application of this technique in the control system for the automatic burdening of a cement production line is given. the debugging method and procedure is introduced. source program written in advanced language, include data buffer access and calling are listed

    文摘:給出了一種「多通道隨機數據流的中斷駐留接收技術方案」 ，詳細描述了內存駐留中斷接收、開設數據緩沖區、數據段地址保存、駐留/解除和數據緩沖區讀取，討論了高級語言程序信息處理，舉出了該技術方案在「水泥生產線微機全自動配料測控系統」中應用的實例，介紹了調試方法和步驟，給出了高級語言讀取數據緩沖區數據及調用源程序。
  5. The performance of data drive technique proposed in this thesis is compared with traditional pipe - line technique, and is proved to be better. the constraint of buffer design is given in this thesis

    在此基礎上，本文進一步提出了一種數據驅動的控制技術，並與傳統的流水線控制技術進行了性能比較，證明了數據驅動控制技術比流水線控制技術的性能更優越。
  6. Chapter 4 explores the multi - level pipeline - controlled parallel mechanism and parallel performance of multi - sharc system. then the parallel data block - processing scheme for distributed multi - dsp ring network system is introduced in view of dsps " macro pipelines and operating pipelines

    提出了在考慮到操作流水線和宏流水線的影響下，數據塊并行處理策略在基於環網結構的分散式多sharc系統中的新應用。
  7. For fast computation of dynamic equations, a special operation unit is referred according to the computing structure of dynamic equations. the pipeline idea is used in this operation unit. there are a adder, a multiplier and a trigonometric function generator in it

    在動力學方程的快速計算方面，根據動力學方程的計算結構提出一種可用於專門計算機器人動力學方程的運算單元，此運算單元採用流水線結構，其運算部分包括加法器、乘法器和一個三角函數發生器。
  8. During the design of vxi - bus serial controller module, the functions of vxi - bus including time - sequence for vxi interface, resource management, interrupt process, bus arbitration, are accomplished. to advance the performance and stability, the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence, the uart, the parameterized baud generator and “ pipeling frame ”. the handle type of data transfer bus for vxi - bus is researched thoroughly, and the format of serial data transfer is designed

    在vxi總線串列控制器設計中，實現了vxi總線控制器的基本功能，包括vxi總線介面時序、總線仲裁、超時處理等;同時利用先進的fpga技術實現了串列總線時序向vxi總線時序的轉換、通用異步收發器（ uart ） 、參數化波特率發生器、流水線結構等功能模塊;在設計中還深入研究了vxi總線數據傳輸的各種操作類型，制定了串列數據傳輸的編碼格式。
  9. ( 2 ) research the instruction launch strategy, controls correlation processing and data correlation processing of 32 - bit mips ’ s double - launching pipeline. obtained the design modes : static launch, optimized compile instruction, 1st pipeline jump and branch processing and double pipeline four channels front data path. ( 3 ) achievement designs by the platform xilinx ise 5. 2i, uses the verilog hardware description language to carry on the design description to the double - launching

    （ 2 ）對基於32位mips架構雙發射流水線的指令發射策略、控制相關處理和數據相關處理等流水線結構的重要問題進行深入研究，並得出了靜態發射、優化編譯指令序、第一流水線無延遲分支處理和雙流水線四通道前向數據通路等一系列能夠與32位mips架構相匹配的雙發射流
  10. Parallel structure of poly - phase decomposition and parallel mixer is applied in the ddc circuit, it solves the bottleneck in mixing and increases the handle speed. the partition of the tuning channel according to the digital mixing sequence, and the ddc by means of decimating first, the low - pass filtering and mixing realize efficiently the down - conversion of the variable carrier frequency band - pass signal. according to the structure of the ddc and the requirement of the frequency

    短數據快速測頻演算法的具體實現:使用并行流水線的設計方法，提高了系統的數據吞吐率，在100mhz的系統時鐘下，能夠實時處理400mhz ~ 600mhz速率a / d采樣的數據，在64點采樣， 100mhz系統時鐘情況下，初次測頻佔用時間640ns ，以後每次測頻佔用時間縮短到160ns ，實時地提供多相濾波下變頻所需的載頻位置信息，縮短了接收機的調諧時間。
  11. General speaking, the large number of signal types to be digitalized has led to a diverse selection of data converters in term of architectures used, bits of resolution achieved and sampling rate employed

    一般而言，大量需要數字化的信號要求有各種不同結構、不同解析度、不同采樣率的a d數據轉換器來實現。在比較了各種模數轉換器的結構和優缺點之後，本項目決定採用流水線式（ pipelined ）的電壓型結構。
  12. The system - controlled iir filter and fft were realized using fpga in this paper, and modified pipeline structure is adopted to greatly raise the running speed in the system - controlled iir filter. in the same time, it is used that the algorithm of n - point complex to compute 2n - point real data block in the radix - 2 fft. it is different to the normal method in the adoption of pipeline single dual ram for each stage

    論文用fpga實現了系統的受控iir濾波器和fft部分，受控濾波器採用改進的流水線結構，運行速度得到了大幅度的提高，同時運用n點復數dft演算法來計算2n點實數數據，在fpga中實現了基2的1024點復數fft ，同一般的實現不同，採用了流水線式的每級單個雙口ram的方法，節省了ram的容量，經驗證，該設計符合濾波器系統的要求。
  13. Around the globe. these features include dynamic load leveling across all available bandwidth, automatic alternate path selection, network - based error detection and recovery, traffic prioritization, data compression, and pipelining

    帶寬的動態測量、網路路徑自動選擇、網路級的錯誤檢測及恢復、數據傳輸的優化、數據壓縮、流水線技術等。
  14. The paper brings forward three buffer design methods, and compares them with each other. the experiment results show that the decoding performance is enhanced by 18. 60 %, and the buffer size is saved by 57. 50 %

    實驗結果表明，採用本文提出的數據驅動控制技術，解碼性能比傳統的流水線技術要提高18 . 60 % ，採用優化的緩存設計演算法，緩存容量節省了57 . 50 % 。
  15. Production data management module is responsible for the management of basic manufacturing data, including basic process data, typical process flow data, equipment and worker data, etc. capability requirement planning module is responsible for the planning of manufacturing resources according to estimate of market demands, supplies the company with data for resource planning. line balancing module is responsible for production line balancing based on the detailed orders, in order to improve the use of manufacturing resources. and facility layout module is responsible for facility layout according to the result of line balancing and the manufacturing data

    生產數據管理模塊負責基礎生產數據的管理，包括製鞋基本工序的管理、標準部件和變型部件的典型工序流程管理、設備和人員數據的管理等等；資源需求計劃模塊根據企業對產品族各個產品的市場需求預測信息以及產品族各個部件對生產能力的需求數據，進行企業資源需求計劃，為企業提供製造資源能力的中長期規劃分析；生產線平衡設計模塊是根據企業的具體產品定單，對產品各個部件的流水生產線進行平衡設計，以提高資源的利用能力；設備優化布局模塊則根據各條生產線的工序要求和設計結果，進行廠房的設備優化布局，降低物流強度，提高流水線的生產效率。
  16. A raw ( read after write ) dependency loop model is developed in this paper to analyze the raw hazards of register operands in complex pipeline. based on this model, a " dynamic " data forwarding policy is suggested to reduce the pipeline stalls caused by data raw hazards. theoretical analysis and practical experiments both show that the average cpi increment caused by data raw hazards can be reduced effectively by the dynamic data forwarding strategy

    對于單發射結構的處理器，降低cpi值的根本途徑在於通過各種軟硬體技術減少流水線的停頓，本文構造了一個raw相關環路模型用於分析流水線中寄存器操作數的raw競爭現象，並提出了一種「動態」數據旁路優化策略，可以最大程度地減少復雜流水線中因數據的raw競爭而導致的互鎖停頓，理論分析和實測結果充分表明「動態」數據旁路機構可以有效地降低流水線因raw互鎖導致的平均cpi增量。
  17. The thesis also introduces the virtual instrument ’ s concept, system architecture, etc. the development of virtual instrument ’ s application software is discussed in detail. it includes virtual instrument software architecture ( visa ), and virtual instrument ’ s software platforms. the thesis discusses the principle and mechanism of work of the simulation of embedded system. by comparing with the principle of traditional logical analyzer, it draw a conclusion that the virtual logical analyzer will work in synchronous way when it is used for both logical state analyzer and logical time analyzer. the thesis

    論文接著探討了嵌入式模擬平臺的原理和工作機制，通過與傳統邏輯分析儀原理的比較，得出了嵌入式模擬平臺下邏輯分析儀無論是做定時分析，還是做狀態分析都工作在同步方式下;並重點剖析了探頭原理，采樣定理和毛刺，數據的建立和保持時間等邏輯分析儀的重要技術指標，得出了虛擬環境對虛擬邏輯分析儀的功能和各項技術指標的影響，還提出了流水線狀態表的思想和實現機制。
  18. This dissertation combines hardware descriptive language, production line transfer technology, ping - pang memory technology and fpga wiring optimization technology to implement data branch and treating

    本文綜合運用硬體描述語言、流水線傳輸技術、乒乓存儲技術、 fpga布線優化技術實現了採集卡的數據分流及處理。
  19. In system hardware design, data pipeline of the separation of reading and writing, which aims at data memory control - flow analysis in raid and reduces the resource ' s expanse of memory system, is established

    在系統硬體設計中，針對數據在raid中的存儲控制流程，建立了讀寫分離的數據流水線，減少存儲系統的資源開銷。
  20. Task assignment optimization for data parallel pipelines in grids

    網格中數據并行流水線的任務指派優化
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