數模譯碼器 的英文怎麼說

中文拼音 [shǔmóyìmǎqì]
數模譯碼器 英文
digital analog decoder
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. Meanwhile, considering of accuracy, complexity and speed, a 6 + 4 segmented architecture is presented. to enhance the speed performance and reduce error and area of dac, the 6 msbs are thermometer - decoded, and the 4 lsbs are binary - weighted

    同時，考慮到數模轉換器的精度、復雜性和速度特性，決定採用電流舵型結構，確定了6 + 4的分段式譯碼方式。
  2. We put the emphases on the soft output viterbi algorithm ( sova ), which is one of turbo code ’ s decoding algorithms, and presents the derivation and computation step of the sova decoding algorithm. after presenting sova and map decoding algorithms and analyzing four kinds of decoding algorithms, the paper makes a comparison among the different decoding algorithms by emulation analysis, and analyzes the time complexity of various algorithms, and then contrasts them. in the last part of this paper, according to the criterion recommended by the consultative committee for space data systems ( ccsds ), including code rate,

    根據空間數據系統顧問委員會（ ccsds ）為turbo碼應用於深空通信系統推薦的標準，包括碼率、碼塊大小、分量碼類型、約束長度、碼生成多項式，以及交織器的選擇等參數的建議以及sova譯碼演算法的理論基礎，設計了sova演算法的實現結構，通過模擬驗證了本文所採用的turbo碼的性能，從而證明turbo碼確實是一種很好的通道糾錯編碼方式，它適用於要求功耗低或信噪比低的深空通信系統中。
  3. The design and application of ad6640 and ad6624 are fully discussed in this part. the design of software module includes the parameter design for ddc filter and the baseband signal processing of dsp. and the realization of the viterbi channel decoding algorithm by dsp and the simulation of the burst at the transmitter are discussed

    模塊的硬體設計主要包括： a d轉換器、數字下變頻器（ ddc ）以及dsp ，詳盡討論了a d器件ad6640和ddc器件ad6624的設計和應用；模塊的軟體設計主要包括： ddc濾波器參數設計和dsp的基帶信號處理，給出了viterbi通道譯碼演算法dsp實現和發射端突發形成的模擬實現。
  4. Both are used to separate the responsibility for rendering pages from the model and controller. both accept objects passed into them as an input argument, both allow inserting string values within code " expressions ", and allow direct use of java code to perform loops, declare variable, or perform logical flows " scriptlets ". both are good ways of representing the structure of a generated object web page, java class, or file while supporting customization of the details

    Jet與jsp非常類似：二者使用相同的語法，實際上在後臺都被編譯成java程序；二者都用來將呈現頁面與模型和控制器分離開來；二者都可以接受輸入的對象作為參數，都可以在代碼中插入字元串值（表達式） ，可以直接使用java代碼執行循環、聲明變量或執行邏輯流程式控制制（腳本） ；二者都可以很好地表示所生成對象的結構， （ web頁面、 java類或文件） ，而且可以支持用戶的詳細定製。
  5. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  6. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。
  7. The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit

    硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。
  8. The first parameter to the postfilter function is the compiled template code, possibly modified by other postfilters

    預濾器函數的第一個參數是編譯之後的模板代碼，該代碼可能被其他一些后濾器修正過。
  9. The fifth chapter analyzes the fixed - point error of bp - based and normalized bp - based decoding algorithm, and gives the final simulation results of each decoding algorithm. with the simulation results and the considering the tradeoff between hardware complexity and error performance, some key parameters and finite precision analysis for the hardware implementation of ldpc decoder have been performed

    第五章對bp - based和normalizedbp - based演算法進行了定點模擬，對ldpc譯碼器的關鍵參數、硬體實現中的定點量化與字長精度問題進行了深入的研究，給出了對譯碼器硬體實現具有參考意義的研究結果。
  10. In retargetable c compiler, all instructions, including parallel instructions, are generated through instruction pattern matching, which is very difficult to generate effective parallel instructions. meanwhile operand type required by parallel instructions is another important factor to restrict generating parallel instructions

    在可重定目標編譯器中，通過指令模板匹配生成目標代碼的方式限制了高效的并行指令的生成，同時，并行指令的操作數類型與單操作指令的要求不一致也是限制并行指令生成的一個重要因素。
  11. This paper achieves expected digital filters program through algorithms descriptions, analyzing and realization, simulation, comparing on error and speed. this paper achieves expected digital interpolations program through algorithms descriptions, analyzing and realization, simulation, comparing on error and speed

    本文應用matlab信號處理工具箱，通過對數字濾波器演算法的描述、演算法分析、實驗模擬、誤差比較，及性能比較，最終獲得滿足要求的數字濾波程序，並編譯成c + +源代碼文件配合主程序調用，完成了系統聯調。
  12. After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance

    經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。
  13. Based on the traditional complier testing, this paper proposes a method that introduces a reference compiler into compiler testing. by collecting dynamic data information ( ddi ) files in software simulator, bugs in tested compiler can be located in function level

    本文最後對編譯系統的驗證進行了研究，提出引入參考編譯器和參考模擬器的測試方法，並通過在模擬器中插裝代碼生成動態數據信息（ ddi ）文件，能夠將錯誤定位到函數級，給編譯器的調試帶來很大的便利。
  14. D a decoder

    數字模擬譯碼器
分享友人
分享到 Line

分享到臉書