時序碼 的英文怎麼說
中文拼音 [shíxùmǎ]
時序碼
英文
sequence code-
According to the least twin multiplication to calculating the sensitivity index in several water production functions. thus, the writer obtains the fitted the value of the sensitivity index and the varied rule. at the same time, the writer puts forward a new method named rag a ( real coding based accelerating genetic algorithm ) and combines raga with dpsa to calculating the best irrigation system under the non - sufficient irrigation of well irrigation rice in sanjiang plain
根據《隨機水文學》理論中的時間序列分析法，建立了適合三江平原井灌水稻需水量預報的非平穩時序隨機模型；通過分析降雨隨機特性，選定季節性時序隨機模型，建立了適合三江平原井灌水稻降雨預報的月平均降雨模型；根據最小二乘法，計算出幾種常用水分生產函數中的敏感指數及敏感系數，進而得到三江平原適宜採用的水分生產函數漠型及模型中敏感指數的變化規律；本文提出遺傳動態規劃法（ raga ? dp ） ，即採用改進的基於實數編碼的加速遺傳演算法（ realcodingbasedacceleratinggeneticalgorithm ，簡稱raga ）與動態規劃法（ dpsa ）相結合，推求非充分灌溉條件下三江平原井灌水稻的最優灌溉制度。The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework
另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。The whole correlation - inheritance coding circuit system is designed, simulated and verified in verilog hdl on the candence systems
採用了硬體描述語言verilog對整個相關繼承矢量量化圖像編碼電路系統在cadence系統上進行了西安理工大學碩士論文設計、模擬及時序驗證。The hardware design which is the basis of the whole design based on sopc cooperates with the nios cpu to accomplish the functions of collecting ts information, detecting errors, and displaying information. the main content in this dissertation includes : ( 1 ) introducing the standard of mpeg - 2 system layer syntax and etr 290 standard about the three levels of detecting parameters ( 2 ) describing the structure and relationship of psi ; designing the hardware implement to accomplish the functions of collecting and analyzing ts information ( 3 ) analyzing and researching the three levels of detecting parameters to accomplish the partition of the hardware and software design, designing the detecting modules cooperated with the software and verifying the functions according to simulation ( 4 ) debugging and testing the design to verify it can achieve our requirements
論文的主要內容包括: （ 1 ） mpeg - 2傳送流系統層的語法規范的介紹和dvbetr290標準中關于對碼流進行三層檢查和監測的參數的介紹; （ 2 ）描述了傳送流特殊信息之間的結構關系，介紹了用硬體方式實現碼流基本信息的提取的設計方法，並將這些信息提供給軟體進行分析處理和結果的顯示，從而實現對碼流提取和分析的功能; （ 3 ）對碼流的三層監測參數進行了分析研究，完成設計的軟硬體劃分，通過硬體設計方式完成對各個監測模塊的開發工作和時序模擬驗證，實現碼流監測功能; （ 4 ）介紹了對碼流基本信息進行提取、分析和碼流檢錯的硬體設計的調試情況和實驗驗證工作，以及最後與軟體設計部分進行聯合調試的情況According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system
針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。Based on the realization of the encoder / decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation. the fprme decoder is advanced in the world. the parallel fec circuit completely conforms to the itu - t protocols, and has important practical value
在rs （ 255 ， 239 ）硬體編碼器/解碼器實現的基礎上，本文按照gpon協議要求，針對gpon中最高速率2 . 488gbps的下行幀，通過設計復雜的操作時序，實現了符合協議規定的32位并行fec編解碼和解擾碼電路，並作了模擬。During the design of vxi - bus serial controller module, the functions of vxi - bus including time - sequence for vxi interface, resource management, interrupt process, bus arbitration, are accomplished. to advance the performance and stability, the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence, the uart, the parameterized baud generator and “ pipeling frame ”. the handle type of data transfer bus for vxi - bus is researched thoroughly, and the format of serial data transfer is designed
在vxi總線串列控制器設計中，實現了vxi總線控制器的基本功能，包括vxi總線介面時序、總線仲裁、超時處理等;同時利用先進的fpga技術實現了串列總線時序向vxi總線時序的轉換、通用異步收發器（ uart ） 、參數化波特率發生器、流水線結構等功能模塊;在設計中還深入研究了vxi總線數據傳輸的各種操作類型，制定了串列數據傳輸的編碼格式。Then, in order to reduce the coding time of each image vector, a fast algorithm based on mean - order - search is proposed. the simulation results of this algorithm show that its coding speed is twenty times faster than that of full search algorithm ( fs ), but its reconstructed image is badly ruined
其次，為減少每個矢量的編碼時間，提出一種基於均值排序碼書的快速搜索演算法，測試結果顯示，該演算法編碼速度是窮盡搜索演算法的二十多倍，但是恢復圖像的質量大大地降低了。The main process includes following : system design, module design, function simulation, time simulation and hardware verification. the whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of uart and the requirement of design. the module design is to design inner circuit structure of each module and uses verilog language to code the code
系統設計是基於uart的實現演算法和設計指標要求，對系統劃分模塊以及各個模塊的信號連接;模塊設計是設計出每個模塊的功能，並用verilog一hdl語言編寫代碼來實現模塊功能;功能模擬和時序模擬使用的工具是以dence的nc _ veri109 ，首先對系統的每個模塊進行功能和時序模擬，模擬通過之後，將整個系統的代碼在外部的輸入埠加上激勵，對整個系統進行功能和時序模擬;硬體驗證是用fpga對系統進行了功能驗證。In this paper we discuss mca circuit, the sequential logic for mca data collection, for the setting of the uld, lld and the gain of pga, as well as the combinational logic for decoding circuits of the computer interface, based on cpld
本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據採集的時序控制邏輯、閾值設定和程式控制放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機介面的譯碼電路等組合控制邏輯。By using the sql server mobile data provider to manage code with the common language runtime, mobile software developers can build highly extensible applications with offline data management capability for disconnected scenarios
通過使用sql server mobile數據訪問介面來管理公共語言運行時代碼，移動軟體開發人員可以利用斷開連接方案的脫機數據管理能力來生成高度可擴展的應用程序。Based on a comprehensive research of image coding algorithm for correlation vq, novel algorithms are presented on two aspects in this paper, and corresponding vlsi coding circuit system is designed, simulated and verified
本論文在對相關矢量量化圖像編碼演算法進行深入分析的基礎上，在兩個方面提出了基於vlsi技術的新演算法，並進行了vlsi硬體設計、模擬模擬和時序驗證。In this paper, the decoding flow of ac - 3 is analyzed, moreover, optimization for software and hardware of decoding of audio. acs real - time decoding will be archieved with ip - based embedded risc core by adding special instructions, such as getbits, max, min and adding hardware for the operation of nop and the optimization of the program
本文分析了ac - 3音頻的解碼流程，並針對音頻解碼進行軟硬體優化，對運用ip技術的嵌入式risc核，通過增加特殊指令getbits ， max和min ，以及增加硬體邏輯完成nop操作和解碼程序的優化，實現了ac3音頻的6聲道的實時解碼。Moreover, video control program to implement internal function of fpga is designed including video capture time sequence control, ping - pang frame buffer read and write time sequence control and lcd display time sequence control, and program ' s simulation and analysis is also provided. at last, this paper presents a portable iv ' s video processing system, and proposes three buffer strategy to control capture buffer. and a moving object detection algorithm of combing an adaptive background subtraction technique with a three - frame differencing is adopted
設計了基於fpga系統結構的車載視頻顯示電路板；利用單片機io口模擬i2c時序，實現了視頻解碼晶元控制；利用fpga實現視頻控制，研究了採集通道時序控制、雙幀存ram讀寫時序控制及lcd顯示時序控制的方法，並進行了軟體模擬和分析；設計了車載視頻檢測系統方案，給出了管理採集緩沖區的三幀緩沖策略，採用綜合三幀差分和自適應背景相減的演算法實現運動檢測，連通體檢測去除虛目標，模擬實驗證明其有效性，同時分析了該演算法在dsp視頻檢測系統中的簡單實現方法。The digital one includes spec, verilog coding, simulation, synthesis, floorplan, routeing, static timing analyze and drc / lvs check
數字電路設計流程則包括：制定spec ， verilog代碼編寫，模擬，邏輯綜合，布局，布線，靜態時序綜合和drc lvs檢查。Design and implementation of memory subsystem unit ; 3. function simulation in three ways : 4. coding optimization for improving the speed of msu
存儲子系統綜合中進行的編碼優化，主要目的是提高設計的速度，使存儲子系統的時序達到設計要求。Then has analysed function 、 port joining 、 inside structure of every module, etc. in detail. using hardware description language to program for function implementation, after function simulation 、 synthesis 、 place and route 、 timing simulation and download, the design is implemented in the spartan 3 serial xc3s400 - 4pq208 chips of xilinx. all procedure of design is worked under the ise 6. 2 integrated environment
接著詳細分析了各模塊的功能、埠連接、內部結構等，並利用硬體描述語言編寫源代碼實現各模塊功能，經過功能模擬、綜合、布局布線、時序模擬、下載等一系列步驟，最終在xilinx的spartan3系列xc3s400 - 4pq208晶元上實現。These sensors make up of a network for signal detection, muti - step transmission is used to transmit the signal, and self - examination is a useful function for each unit. 2
三種傳感器在一定范圍內組成一個探測網路，網路中的各探測單元利用自行設計的多級傳輸的方法傳遞信息，解決了傳輸中的編碼及時序問題，設計了具體電路。Elements are executable statements, which constitute the run - time code of your program
過程級元素的大多數內容都是可執行語句，它們組成了程序的運行時代碼。分享友人