時序邏輯系統 的英文怎麼說

中文拼音 [shíxùluóxìtǒng]
時序邏輯系統 英文
sequential logic system
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 系 : 系動詞（打結; 扣） tie; fasten; do up; button up
  • 統 : Ⅰ名詞1 （事物間連續的關系） interconnected system 2 （衣服等的筒狀部分） any tube shaped part of ...
  • 時序 : [地質學] sequence; sequential; time sequence; timing sequence; sequence in time
  • 邏輯 : logic
  • 系統 : 1. （按一定關系組成的同類事物） system 2. （有條理的;有系統的） systematic
  1. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  2. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  3. In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework

    另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。
  4. The dcs of i / a series is regarded as main reference object, and the control is separated from model. and the configuration of control is operatised at administration system, not to be added into model, not to build control sound code also. therefore it realizes on - line adjusting, real - time control and so on. users configurate by filling table. they only define i / o condition, fill certain operation variable, and name logic variable. the software offers a friendly user ' s interface, so personnel can compile and modify the control and logic program, change the value of logic and control variable conveniently, attach themselves to run, debug and control the system, not need to know the programs deeply. so the configuration software offer a flat that control engineers can attend to control loop, not to give their attention to the complicated program

    在本課題中，採用填表的方式進行控制組態，用戶只需定義i / o條件、填寫具體的運算變量名即可。本軟體為建模人員提供了一個友好的用戶界面，使建模人員在建模時不必對模塊內部的控制、邏輯程序有很深的了解就可以方便的對其進行編寫和修改，實時改變各邏輯和控制變量在數據庫里的值，參與運行和調試，從而實現對系統的控制。因此，本組態軟體提供的這樣一個平臺，讓控制工程師能集中精力于控制迴路的構成，而不必拘泥於一些具體而煩瑣的程序操作。
  5. In this paper, interval temporal logic is applied to represent the hybrid systems

    本文運用間斷式時序邏輯表達和建立水工業系統模型。
  6. The systems are usually described by the timed automata and the properties are specified by the temporal logic

    這類系統通常用時間自動機來表示，而它們的性質則用時序邏輯公式表示。
  7. For seminal work introducing temporal logic into computing science and for outstanding contributions to program and systems verification

    他將時序邏輯引入計算機科學，為程序和系統的檢測驗證方面提供一種有力的工具。
  8. Complex programmable logic device ( cpld ), usually used to develop asic, is widely used in digital system to accomplish complex combinational and sequential logic

    復雜的可編程邏輯器件（ cpld ）廣泛地用於數字系統中，常用作設計自己的專用集成電路，可實現復雜的組合邏輯和時序邏輯。
  9. The tool mr barth is employing to effect this transition is linear temporal logic, a system of mathematical logic that can express detailed constraints on the past and the future

    巴斯先生用來實現這一轉化過程的工具是線性時序邏輯，一種可以表達過去和未來的詳細約束的數理邏輯系統。
  10. The thesis analyses the problems on the noise of apd photoelectric receiving system. author designs apd laser signal receiving system circuits, front amplify circuit, controlling time - series logic circuits, dc / dc transform circuits. and takes apd bias voltage fuzzy control

    分析了apd光電接收系統的噪聲問題，並對apd激光信號接收系統電路、前置放大電路、控制時序邏輯電路、 dc / dc變換電路進行了設計，採取了apd偏壓模糊控制。
  11. After discuss the structure and character of operating system qnx and inter - process communication between pc ' s running qnx or windows, the paper describes the structure, function and flow chart of mission planning software which is developed in qnx, and narrates the course of simulation co - debug experiment, dynamically showing the results of the mission planning in the case of " ocean physiognomy reconnaissance ", and proving the logical correctness and feasibility of task serial produced by mission planning

    在論述了多任務、實時操作系統qnx的結構特點以及基於qnx與windows運行的pc機之間網路進程通信的基礎上，本文描述了在qnx上開發的使命規劃軟體的結構功能和流程圖，並敘述了模擬聯調實驗的過程，動態地顯示了「海洋地貌勘測」這一案例使命規劃的結果，並證明了使命規劃所得的任務序列在實際運行中邏輯的正確性與可行性。
  12. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  13. It includes : dynamic show of technics flow, real time data acquirement and show, history data save and print, fault alarm, etc. the plc control system mainly accomplishes the wastewater technics flow control, harmonizes the logical relationship among local intelligent control instruments and transmits the state of each local equipment to the industrial computer simultaneously, the plc control station receives the control commands from the industrial computer ; the local intelligent units take charge of the correlated parameters measure, disposal and control, and it will transmit the related parameters to the computer, etc. in this thesis, introduced municipal wastewater treatment technics, the integrated application program development of computer, the design method of plc control station, the communication between plc control system and computer, and the network of wastewater treatment with profibus - dp was also discussed

    上位計算機主要實現遠程監測和管理功能，具體包括:工藝流程動態顯示、實時數據獲得及顯示、歷史數據存儲與列印、故障報警等功能plc控制系統主要完成工藝流程式控制制以及協調現場各智能儀表之間的邏輯關系，將現場各設備的運行狀態通過通訊網路傳輸到上位計算機，並接收上位計算機的控制指令;現場各智能儀表單元負責各相關參數的監測和處理、控制，並將有關參數送往上位監控計算機進行處理、保存等。本文以莎車污水處理項目為例，介紹了城市污水處理工藝、上位監控計算機的綜合應用程序開發、城市污水處理自動控制系統plc控制站的設計和採用profibus系列中廣泛應用於現場設備的profibus - dp總線。
  14. And, the thesis mainly presents the research on the key technique of the dataflow control, including the realization of the pci interface control, the control of the sram memory that read or written by fpga, the pretreatment and the output control of the image and the intercommunication between pc and fpga. and then, it presents the design and the realization of the pc application program. in the end, it presents the debugging stepps and the application of the system.

    本文的重點在於介紹高解析度實時圖像處理系統的fpga控制邏輯設計，主要研究了該數字圖像處理系統中影響系統實時處理速度的數據流控制技術，如pci介面控制、 fpga與外部ram的高速讀寫控制、圖像的採集預處理，圖像的輸出控制等，本文還介紹了高解析度實時圖像處理卡的上位機應用程序設計與實現，本文的最後介紹了系統的調試及應用。
  15. We use temporal logic language xyz / e as our component description language for components may have different abstract hierarchy and different granularity. xyz / e is able to describe the dynamic semantics and static operations of component, and to formally describe system in different hierarchy

    由於構件可能具有不同的抽象層次和粒度，我們採用了時序邏輯語言xyz e作為構件描述語言，這種語言能夠描述構件的靜態語義和動態執行，並且能在不同抽象層次上對系統進行形式化描述。
  16. The broadband signal is generated by high speed d / a, and the logical control of the system such as the interface timing control of ide or sdram is implemented by fpgas

    採用高速d / a實現輸出信號的高寬帶，採用多片fpga完成整個系統的時序邏輯控制，比如ide介面時序的實現， sdram的操作等。
  17. In data sampling circuit, high - speed, complex programmable logic device cpld technique is used. high - speed double - port ram, control sampling time sequence logic, cpu interfaces and bus circuit are implemented in cpld. sampling speed is up to 80mhz, sampling depth is ik - byte, and cpld can fulfill the requirement of the software arithmetic to sampling

    在數據採集電路中採用了高速復雜可編程邏輯器件cpld技術，晶元內設計有高速雙埠ram 、控制采樣時序邏輯及cpu介面、總線等電路，采樣速率高達80mhz ，采樣深度1k位元組，很好地解決了超聲波微位移傳感器軟體演算法對采樣的要求，並可實現在線升級，大大提高了系統的整體性能。
  18. The method of model checking is a formal verification technique using the method of state - space search to verify if the behaviors of a given system ( the model ) satisfy a certain property that represented by temporal logic formulas, while the system presented as a kripke structure

    它通常採用狀態空間搜索的方法來檢測一個給定的計算模型是否滿足某個用時序邏輯公式表示的特定屬性。它是一個自動檢驗有限狀態並發系統的技術。
  19. The thesis aims to give a scheme of designing a 48 - channel collected seismic recorder based on pci bus, and a testing machine has been completed in the basis of the scheme. pci bus provides a high data transfer speed, which solve the problem of transfering a mass of data in a short period of time ; moreover, two assistant channels are provided to sample reference signal ; the function of data correlation in real - time is also provied in the software of the instrumental system

    論文論述了pci總線功能介面的實現和數據採集模塊的設計，給出了利用pci9054介面晶元設計pci介面的詳細過程，並利用driverstudio為pci數據採集系統編寫了設備驅動程序;在數據採集模塊的設計中，主要完成的工作有多通道數據採集、浮點放大以及系統的低噪聲設計，並利用cpld設計了整個系統的時序邏輯。
  20. Based on these, this paper explores a new way which combines the visual modeling language and formal method to describe software architecture through combining uml 2. 0 and xyz / adl. in this paper, the disadvantage of several main methods of software architectural description is analysed, the advantage of uml 2. 0 compared with uml 1. x in the software architecture description is analysed, the corresponding relationship between uml 2. 0 and xyz / adl in the architectural description is given and uml 2. 0 model elements which used to describe the according architectural conception are determined, then a new way to describe software architecture which combine uml 2. 0 and xyz / adl through defining the semantics of xyz / e for uml 2. 0 is composed. in order to realize this method, the formal semantics of uml 2. 0 sequence diagram and state diagram based on xyz / e are defined. in final, the arcitectural description of a simple dask manager system which uses our method is given

    本文分析和比較了當前國內外常用的軟體體系結構描述方法，指出了它們各自存在的問題;分析了uml2 . 0與uml1 . x相比在軟體體系結構描述方面的優勢，確定了用uml2 . 0描述軟體體系結構概念元素所使用的相關模型元素，給出了uml2 . 0與xyz / adl在體系結構描述中的元素對應關系;提出了一種通過定義uml2 . 0相關視圖的xyz / e語義，把uml2 . 0與xyz / adl結合起來描述軟體體系結構的新方法，並分別定義了uml2 . 0的順序圖和狀態圖的xyz / e時序邏輯語義;最後通過對一個簡單的任務管理系統的體系結構進行描述，把本文提出的結合思想運用到實例系統的描述當中。
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