時序邏輯電路 的英文怎麼說

中文拼音 [shíxùluódiànlù]
時序邏輯電路 英文
sequencial logic circuits
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 時序 : [地質學] sequence; sequential; time sequence; timing sequence; sequence in time
  • 邏輯 : logic
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. The method of connecting timing into 1ogic i s explained in waveform po1ynomia1 on the basis of waveform concept in boo1ean process theory. and an ana1ytica1 de1ay mode1 that is close to practice circuits is found

    並在布爾過程論中定義波形的基礎上，說明了邏輯與時序在波形多項式中的結合方法，建立了接近實際電路的解析延遲模型。
  2. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  3. These character based on sichuan power network ' s practice operation experience, in allusion to the config of the carrier wave protection in bypass breaker operating, through the study of protection ' s typical config : one side lfp - 902a, one side csl - 101a, proceeded comprehensive act module test, noted plenty of first hand test data and wave picture, proceeded detailed theory analyses, plenitude demonstration atresic type carrier wave distance protection when twain side atresic type logic is not completely same, basically can fill power network ' s requirement to relay of reliability selectivity speedly and sensitively

    本文結合四川電網的實際運行經驗，針對旁路開關代路運行時的保護配置情況，通過對旁路代路時保護典型配對組合：一側lfp - 902a ，一側csl - 101a的保護配置情況的深入研究，做了全面的動模試驗，記錄了大量的第一手試驗數據和波形，進行了詳細的原理分析，充分驗證了高頻閉鎖式距離零序保護在兩側閉鎖式邏輯不盡一致的情況下，基本能夠滿足電網對繼電保護的可靠性、選擇性、快速性以及靈敏性的要求。
  4. In fact, we use the digital way directly to synthesize sine wave

    摘要數字電路技術課程的知識難點是時序邏輯電路的設計。
  5. The thesis offers apd signal amplify circuit chart and controlling time - series logic circuit principle chart bearing practical applied value

    給出了apd信號放大電路和控制時序邏輯電路原理圖。
  6. It is easier for us to realize the hardwave circuit, and the content of sine wave at least by 45db is the projecting advantages

    本文主要論述一種實用的時序邏輯電路的設計與實現設計一個十字路口交通燈自動循環亮滅的控制器。
  7. Complex programmable logic device ( cpld ), usually used to develop asic, is widely used in digital system to accomplish complex combinational and sequential logic

    復雜的可編程邏輯器件（ cpld ）廣泛地用於數字系統中，常用作設計自己的專用集成電路，可實現復雜的組合邏輯和時序邏輯。
  8. The thesis analyses the problems on the noise of apd photoelectric receiving system. author designs apd laser signal receiving system circuits, front amplify circuit, controlling time - series logic circuits, dc / dc transform circuits. and takes apd bias voltage fuzzy control

    分析了apd光電接收系統的噪聲問題，並對apd激光信號接收系統電路、前置放大電路、控制時序邏輯電路、 dc / dc變換電路進行了設計，採取了apd偏壓模糊控制。
  9. Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single - period sensitization is proposed. compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high - speed circuit design

    在時序邏輯電路精確定時方面，從時序電路的敏化定理出發，使用本文給出的條件可敏化概念，通過對通路敏化性質的判斷建立了一種新的單周期敏化的時序電路最小時鐘周期精確確定方法。
  10. Digital circuit includes two kinds - the assembly logic circuit and the sequential logical circuit, the characteristic of the assembly logic circuit is that the output signal is only the function which enters the signal and has nothing to do with the entering state at any other moment, it has no function of memory

    摘要數字電路分為組合邏輯電路和時序邏輯電路兩類，組合邏輯電路的特點是輸出信號只是該時的輸入信號的函數，與別時刻的輸入狀態無關，它是無記憶功能的。
  11. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  12. Therefore it comes true the on - line adjusting, real - time control and so on. it sames as real locale. the software of logic protect ( include electric logic ) and control includes some usual algebraic and operation model of thermal control and logic operation of logic protect. it adopts foxboro ' s dcs as a example, so we configuration via filling table, user only define i / o condition, fill certain operation variable, and name logic variable. the software offers a friendly user ' s interface, personnel can compile and modify the control and logic program, change the value of logic and control variable conveniently, attach themselves to run, debug and control the set, not need to know about the inside of the old programs deeply. so the configuration software offer a flat that control engineer can attend to the structure of control loop and logic protect ( include electric logic ), not but to handle complicated program

    它以foxboro的dcs控制系統為主要參考模式，採用填表的方式進行控制組態，用戶只需定義i / o條件、填寫具體的運算變量名、邏輯變量名即可。本軟體為建模人員提供了一個友好的用戶界面，使建模人員在建模時不必對模塊內部的控制、邏輯程序有很深的了解就可以方便的對其進行編寫和修改，實時改變各邏輯和控制變量在數據庫里的值，參與運行和調試，從而實現對機組的控制。因此，本組態軟體提供的這樣一個平臺，讓控制工程師能集中精力于控制迴路及邏輯保護（包含電氣邏輯）的構成，而不必拘泥於一些具體而煩瑣的程序操作。
  13. In this paper we discuss mca circuit, the sequential logic for mca data collection, for the setting of the uld, lld and the gain of pga, as well as the combinational logic for decoding circuits of the computer interface, based on cpld

    本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據採集的時序控制邏輯、閾值設定和程式控制放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機介面的譯碼電路等組合控制邏輯。
  14. In data sampling circuit, high - speed, complex programmable logic device cpld technique is used. high - speed double - port ram, control sampling time sequence logic, cpu interfaces and bus circuit are implemented in cpld. sampling speed is up to 80mhz, sampling depth is ik - byte, and cpld can fulfill the requirement of the software arithmetic to sampling

    在數據採集電路中採用了高速復雜可編程邏輯器件cpld技術，晶元內設計有高速雙埠ram 、控制采樣時序邏輯及cpu介面、總線等電路，采樣速率高達80mhz ，采樣深度1k位元組，很好地解決了超聲波微位移傳感器軟體演算法對采樣的要求，並可實現在線升級，大大提高了系統的整體性能。
  15. For examp1e, the sort arithmetic so1ves 1eve1 partition of combination 1ogic ; the computing input waveform of sensitized path makes the possib1e of conf1rm the minimum c1ock circ1e ; the cyc1e - - based method for synchronous op tajg1fyjct7 : @ + $ { 4it x sequentia1 circuits improve the speed of waveform simu1at ion

    其中，編排級數法確定了組合邏輯的層次關系；通路敏化輸入波形方法決定了最小時鐘周期；基於周期的同步時序電路的模擬演算法加快了模擬的速度等。
  16. Since high performance control logics are usually hard for non - scan test generation, dft structures could be embedded as offsets in tradition, while it will cause manufacturing cost increase and performance overhead. in this paper, an indirect test generation method based on retiming is proposed, which could dramatically reduce the cost of non - scan atpg without any loss of original optimized attributes. experiments on some iscas 89 benchmarks show the benefits of our approach in enhancing atpg of performance - driven logic

    對性能驅動控制邏輯進行測試生成難度較大，通常要加入可測性結構，但會影響原電路優化性能並增加生產成本.本文以重定時理論為基礎，提出了對高性能時序電路進行間接測試生成的方法，這種方法在不影響原電路任何優化特性的前提下，可顯著降低測試生成時間，提高測試生成質量.在iscas 』 89部分基準電路進行實驗，結果證明了其有效性
  17. Mostly, this design employs mentor corporation software " fpga advantage " as exploitation tool to perform design input 、 simulation and logic thesis with every level and every model to finish the fore design ； then, choices the xilinx corporation product xcv1000 of the vertex series and employ its tool “ allicance series ” to implement layout and timing simulation

    設計主要採用menter公司的功能強大的fpgaadvantage作為開發工具，進行了各個層次、各個模塊的設計輸入、模擬以及邏輯綜合，完成了電路的前端設計；然後選用xinlinx公司的fpga的vertex系列的xcv1000 ，用xinlinx公司的allianceseries工具，進行布局布線，然後再進行時序模擬，生成配置文件。
  18. The digital one includes spec, verilog coding, simulation, synthesis, floorplan, routeing, static timing analyze and drc / lvs check

    數字電路設計流程則包括：制定spec ， verilog代碼編寫，模擬，邏輯綜合，布局，布線，靜態時序綜合和drc lvs檢查。
  19. According to the redundancy in digital circuits, we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits. to erase the redundant transition of the clock, the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design

    為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計並應用於時序電路設計中。
  20. The thesis includes the design of hard circuit, pcb ( printed circuit board ), driver and application soft involving a / d board and d / a board. the detailed functional modules consist of multiplex signals select module 、 analog digital conversion module 、 digital analog conversion module 、 pci protocol conversion module 、 driver and magnifying module 、 control logic 、 clock circuit and configuration circuit. the importance of the thesis is a / d board

    本課題包括硬體電路、印刷電路板（ pcb ） 、驅動程序和應用軟體的設計，涉及a / d板和d / a板兩大塊部分，具體的功能模塊包括多路信號選擇模塊、模數轉換模塊、數模轉換模塊、 pci協議轉換模塊、驅動放大模塊、控制邏輯、時鐘電路和配置電路，其中重點是a / d板部分。
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