時鐘信號發生器 的英文怎麼說

中文拼音 [shízhōngxìnháoshēng]
時鐘信號發生器 英文
clock signal generator
  • : shí]Ⅰ名1 (比較長的一段時間)time; times; days:當時at that time; in those days; 古時 ancient tim...
  • : Ⅰ名詞1 (用銅或鐵製成的響器) bell 2 (計時器) clock 3 (指鐘點、時間) time 4 (沒有把兒的杯子...
  • : 號Ⅰ名1 (名稱) name 2 (別號; 字) assumed name; alternative name3 (商店) business house 4 (...
  • : 名詞(頭發) hair
  • : Ⅰ動詞1 (生育; 生殖) give birth to; bear 2 (出生) be born 3 (生長) grow 4 (生存; 活) live;...
  • : 名詞1. (器具) implement; utensil; ware 2. (器官) organ 3. (度量; 才能) capacity; talent 4. (姓氏) a surname
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬調理模塊對輸入的進行調理,以達到系統和模數轉換( adc )采樣的要求; dsp作為系統的核心部件,外擴了adc 、以太網控制、 rs - 485總線收、 can總線收晶元, dsp對實數據進行處理,當報警將實數據通過以太網上傳給上位機。
  2. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll (延遲鎖相環)實現usb2 . 0收宏單元utm的恢復模塊。其中pll環路構成的將外部晶振的12mhz正弦成60mhz 、 120mhz 、 480mhz等本地。 dll環路依據本地對外部數據進行恢復。
  3. Controllable rsfq timing pulse generator

    可控時鐘信號發生器
  4. The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation

    再次,我們對整個cmos數字圖像傳感進行了電路設計,主要包括:時鐘信號發生器,順序移位寄存和像素陣列。
  5. This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution

    主觸邏輯在20m下以流水線的方式工作,保證沒有死間的產。第二個例子是任意數字的設計。
  6. The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions

    本文論及的「」概念不是指日常活中使用的表,而是由產基準頻率的(如銫原子頻率標準、銣及高精度石英晶體振蕩等)中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定功能的綜合體。如bits就是一種設備,它提供用在通系統中控制某些功能的定間基準設備,提供的稱為基準、定或同步
  7. The signal collecting system of singlechip collects the signals from generator. the paper introduces the every part of the singlechip. the key component is a 8051cpu, its surrounding circuits include dc power source, simulating signal collecting circuit, digital signal collecting circuit, a / d converting circuit, clock generating circuit, counting frequency circuit, controlling circuit, communicating circuit, and some other circuits

    前臺單片機採集系統完成對電機組多息量的採集,本文詳細介紹了電路設計,系統的核心件為8051cpu ,其外圍電路包括電源電路、模擬採集電路、 a d轉換電路、數字採集電路、電路、測頻電路、控制電路、通訊電路等。
  8. Within this scope, users can get almost any frequency clock by configuring the register, as the tune - process is nearly continual ( in fact there are many discrete frequency points ). the main circuit of the clock generator is a cppll ( charge pump pll ) designed in a method

    可以向系統提供頻率范圍是93 . 75k - 180mhz的,用戶可以通過配置寄存的方法使輸出自己需要的頻率,而且這一調頻過程幾乎是連續的(實際上是眾多離散點構成的線性近似) 。
  9. A monolithic clock synthesis pll, which is expected to be a reference 800mhz clock generator in accelerometer system, has been designed and characterized in this paper

    本文設計了一種採用鎖相環頻率合成技術實現的800mhz,用作加速度傳感讀出電路的基準
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