時鐘抖動 的英文怎麼說

中文拼音 [shízhōngdǒudòng]
時鐘抖動 英文
clock jitter
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 抖 : 動詞1 （顫動;哆嗦） tremble; shiver; quiver 2 （振動; 甩動） shake; jerk 3 （振作; 鼓起精神） rou...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 抖動 : （顫動; 用手振動）1 shake; tremble; vibrate; chatter 2 agitation; joggling; whipping; flutter; ji...
  1. Thirdly, the paper discusses the driver of the peripheral equipment, how to port the uc / os - n and uclinux, h. 323 protocol and the application of the system in the digital speech classroom. also some software and hardware measure are adopted to enhance the system stability. at last, the shortcoming and the something to be improved are given. dsp can be used to realize real - time speech coding algorithm, and after porting ( ac / os - n, arm can manage the keyboard, the lcd and the ethernet peripheral etc. then the embedded network system with specific purpose can be used in others fields, such as pda, set of top, web tv, ect

    在實際設計實現中，為提高系統軟、硬體整體穩定性和可靠性，使用了以下幾種方法： （ 1 ）低電壓復位、抗電源抖動能力、增加時鐘監測電路、抗電磁干擾能力、散熱等技術； （ 2 ）多層pcb設計，線路板結構緊湊，電源部分採用數字5v 、 3 . 3v 、 3v 、 1 . 8v和模擬5v多電源供電； （ 3 ）選用表面貼和bga封裝的器件； （ 4 ）按照軟體工程的要求進行系統分析，規劃系統框圖、流程分析、模塊劃分，減小了不同模塊的相關性，從而最大限度避免了錯誤的發生。
  2. In the last part of this paper, simulation is given to show the performances of the clock recovery methods. the results prove the good jitter performances of the methods

    從模擬結果可以看出，同步時鐘統計恢復法具有很好的抖動性能，可以作為gpon系統tdm接入的一種高效時鐘恢復方案。
  3. Clock recovery is an important and difficult part of tdm access, so the thesis will emphasize on it. and two methods of clock recovery are proposed in the thesis

    然後，本文對同步時鐘統計恢復法進行了分析，推導出了時鐘信號低頻抖動的時域和頻域特性公式，並利用matlab對低頻特性進行了模擬分析。
  4. Oscillator generated a wave with frequency 132 khz as the clock signal

    振蕩器電路產生一個頻率在132khz附近抖動的矩形波作為整個電路的時鐘信號。
  5. The paper compares some algorithms on rs decoding, makes improvements based on the me algorithm, removes the modifying step in decoding truncate rs code, corrects unsuitable statements in the related papers, and parameterizes the rs decoding module, reducing its area by 20 %. the paper overcomes the signal integration problem in multi - clock design, greatly lowers the phase jitter without area increase, introduces pll to adjust rate for the first time, and parameterizes the module

    本文比較了實現rs解碼的幾種演算法，並在me演算法基礎上進行改進，創造性的去掉了縮短碼解碼中的校正環節，糾正了有關論文中的不當論述，並將rs解碼模塊進行了參數化設計，同時也將rs解碼的規模縮小了20 ；克服了多時鐘設計中的信號完整性難題，在沒有增加模塊面積的條件下，大幅降低數據的相位摘要抖動，首次引入鎖相環來調整速率。
  6. It was satisfied for performance testing of high - speed a / d circuit in the project assess the factors of reducing a high speed a / d circuit performance were found out, such as harmonic distorted in front analog circuit, . sample clock shaking, analog power and the noise in ground plane etc

    並在試驗測試的基礎上找出了影響高速模數轉換電路轉換性能的幾個主要的因素，即：前端運放電路諧波失真、采樣時鐘抖動、模數電源及共地噪聲串擾等。
  7. Rc and other relaxation oscillators just will not do since amplitude noise in whatever circuit functions as a comparator will appear as phase noise on the output signal

    Rc諧振器以及其它一些張弛振蕩器不能滿足要求，這是因為它們的核心是電壓比較器，需要利用電壓信號的波動（噪聲）來獲得穩定的輸出，這種波動就構成了時鐘的抖動。
  8. Based on all these above, two schemes which use digital methods to measure the jitter of a pll clock of 2. 048mhz are presented and accomplished

    在此基礎上，提出並實現了測試一固定頻率（ 2 . 048mhz ）鎖相時鐘抖動的方案。
  9. The sampling clock generator must also have adequate spectral purity

    時鐘發生電路固有的抖動應該足夠小。
  10. Figure 5. 36 shows the relationship between sampling clock jitter and snr previously presented

    圖5 . 36顯示了采樣時鐘抖動和信噪比之間的關系。
  11. The adc aperture jitter must be minimal, and the sampling clock generated from a low phase - noise quartz crystal oscillator

    Adc的孔徑抖動必需盡可能的小，而且要使用低相位噪聲的石英晶體振蕩器作為采樣時鐘發生器。
  12. Timing jitter in satellite data modem

    衛星數字數據機中的時鐘抖動
  13. At the same time, the influence of the parameter - estimating error and the noise on amplitude of the signal are discussed, and simulation was performed to validate the analysis result

    同時，還從理論上分析了參數估計誤差和信號幅度噪聲對測量時鐘抖動的影響，並進行了模擬驗證。
  14. The effects of sampling clock jitter on signal - to - noise ratio ( snr ) and effective bit ( enob ) performance discussed in section 3 are even more dramatic in undersampling applications because of the higher input signal frequencies

    在第三章討論的采樣時鐘抖動對信噪比和有效位性能的影響在欠采樣應用中因為更高的輸入信號頻率顯得更有戲劇性。
  15. Clock jitter measurement technique based on signal - to - noise ratio

    基於信噪比測量時鐘抖動的方法
  16. I set his plate to keep warm on the fender ; and after an hour or two he re - entered, when the room was clear, in no degree calmer : the same unnatural - it was unnatural - appearance of joy under his black brows ; the same bloodless hue, and his teeth visible, now and then, in a kind of smile ; his frame shivering, not as one shivers with chill or weakness, but as a tight - stretched cord vibrates - a strong thrilling, rather than trembling

    我把他的盤子放在爐柵上熱著，過了一兩個鐘頭，他又進來了，這時屋裡人都出去了，他並沒平靜多少：在他黑眉毛下面仍然現出同樣不自然的的確是不自然的歡樂的表情。還是血色全無，他的牙時不時地顯示出一種微笑他渾身發抖，不像是一個人冷得或衰弱得發抖，而是像一根拉緊了的弦在顫動簡直是一種強烈的震顫，而不是發抖了。
  17. The result shows that the parameter - estimating method can measure not only the value of jitter, but also its distribution

    結果表明，採用參數佑計測量法測量時鐘抖動，不但能夠準確地測出抖動的大小，而且能夠測出抖動的分佈。
  18. Dba design can enhance the dll circuit ' s robustness and minimize the clock jitter. it also avoids the difficulty of analog parameter design and process control

    採用這樣的設計，增加了dll電路的穩定性，減小了時鐘抖動，同時避免了模擬電路參數設計和工藝控制的難點。
  19. The relationship between the clock jitter and the sampling sequence of a sine wave is studied, and a new method to measure the jitter and distribution of a clock signal with pico - second resolution is proposed using adc sampling based on estimating method of the parameters in sine signal

    摘要研究了時鐘抖動與正弦信號的采樣序列之間的關系，並在正弦信號參數估計法的基礎上，提出一種利用adc采樣測量皮秒量級的時鐘抖動大小和分佈的新方法。
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