時鐘控制信號 的英文怎麼說

中文拼音 [shízhōngkòngzhìxìnháo]
時鐘控制信號 英文
clock control signal
  • : shí]Ⅰ名1 (比較長的一段時間)time; times; days:當時at that time; in those days; 古時 ancient tim...
  • : Ⅰ名詞1 (用銅或鐵製成的響器) bell 2 (計時器) clock 3 (指鐘點、時間) time 4 (沒有把兒的杯子...
  • : 動詞1 (告發;控告) accuse; charge 2 (控制) control; dominate 3 (使容器口兒朝下 讓裏面的液體慢...
  • : Ⅰ動詞1 (製造) make; manufacture 2 (擬訂; 規定) draw up; establish 3 (用強力約束; 限定; 管束...
  • : 號Ⅰ名1 (名稱) name 2 (別號; 字) assumed name; alternative name3 (商店) business house 4 (...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 控制 : control; dominate; regulate; govern; manage; check; cybernate; manipulate; encraty; rule; rein; c...
  1. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準產生模塊、 d a編碼模塊、 i ~ 2c總線模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視實現視頻解碼; fpga視頻處理模塊對解碼后的數據進行去噪處理的同還負責系統的邏輯;視頻數據幀存模塊為大量高速的視頻數據提供緩沖區;基準產生模塊通過輸入基準視頻為系統提供精確的相關同步; d a編碼模塊在視頻處理模塊的下把數字視頻數據轉換成復合電視供顯示用: i ~ 2c總線模塊模擬i ~ 2c總線序實現對系統中編、解碼晶元的初始化。
  2. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬調理模塊對輸入的進行調理,以達到系統和模數轉換器( adc )采樣的要求; dsp作為系統的核心部件,外擴了adc 、以太網器、 rs - 485總線收發器、 can總線收發器和晶元, dsp對實數據進行處理,當報警發生將實數據通過以太網上傳給上位機。
  3. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法,重點介紹了視頻數字化技術、抗混疊濾波器、箝位、增益、鎖相技術、同步產生、電視亮色分離、彩色解碼等技術,這些關鍵技術為視頻的數字化處理提供了重要的基礎。
  4. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影( dsa )成像系統的組成結構和數據流向進行了深入研究和分析,並對系統中的數據流向進行了完整的歸納和總結,給出了x線數字成像系統中的高速大容量數據通道的設計方案;在對sdram的方式做了深入探討后,給出了實現大容量多條sdram共同工作的解決方案,在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲;通過對pci總線介面的深入研究,優化後端狀態機設計和低層驅動程序開發,給出了完整的pci介面方案實現高速dma數據傳輸,完全可以滿足視頻傳輸要求;深入研究了基於大規模可編程器件的數字系統設計方法,針對通用fifo使能漂移、輸出數據難于建立和保持等設計難點,提出了利用fpga中的鎖相環提供多個相移的來提高系統穩定性的解決方案,從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  5. Above all, [ 12 : 8 ] harming error correction theory is mentioned in this paper. the edac circuit designed by vhdl can works normally at different frequency of the cpu clock such as 66mhz 50mhz 40mhz 33mhz. the edac function of the circuit can also be disabled by software tool. meanwhile, some basic devices such as and logic, or logic, not logic and some small scale integrated circuits are also integrated in the fpga

    本論文闡述了12 , 8漢明碼糾錯設計過程,採用vhdl語言實現糾錯編碼器( edac ) ,本設計能夠適應cpuclk2的不同頻率,如66mhz 、 50mhz 、 40mhz 、 33mhz ,並且能夠通過軟體的使fpga的糾錯編碼功能關閉。
  6. Gps is a planet wireless conductance system which is global and all - weather, gps can offer high precision time orientation information to infinite user, clock precision reachs 10 ? 6 magnitude 。 not only changes traditional time method of quartz crystal clock, but also replaces wireless shortwave and even more lowfrequency signal and tv signal whose overlay range is limited and low precision, offers advantage to geology field task, achieve automatization and high precision of seismic flow observation

    利用gps授全方位、全天候、連續性、實性和高精度的特點,以gps為基準來校準本地(晶體振蕩或原子) ,將gps接收機輸出的長期穩定度和恆溫晶振的短期穩定度相結合,應用大規模可編程邏輯器件,設計和實現了由pc104的實在線授系統。
  7. The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions

    本文論及的「」概念不是指日常生活中使用的表,而是由產生基準頻率的發生器(如銫原子頻率標準、銣及高精度石英晶體振蕩器等)中的某種頻率源以及相配套的輸入、輸出介面和電路等組成的一整套具有特定同步定功能的綜合體。如bits就是一種設備,它提供用在通系統中某些功能的定間基準設備,提供的稱為基準、定或同步
  8. Furthermore, low power flip - flop design by reducing the short - circuit power which relates with clock overlapping is also mentioned in this paper

    此外,由於觸發器的短路功耗和觸發器的的交迭程度有關,因此文章還對通過合理規劃的交迭來達到減少觸發器短路功耗的低功耗觸發器結構進行了討論。
  9. Bits supplies the synchronous timing signal to these equipments inside the telecommunicationt building, such as dps, atm, no. 7, dxc, tm & adm in sdh, don and in etc. the related techniques are involved in the content of synchronization ne twork, timing distribution, the timing signal transportations x impairments etc. the second chapter tells the structure and the function of the building integrated timing system. the third chapter summarizes the digital synchronization network techniques, which emphasizes the basic concept of synchronization networks analyzes the necessity of building the synchronization network and introduces all kinds of synchronization methods. the fourth chapter represents the transportation of the synchronization signal

    本文第二章講述了通樓綜合定系統的構成及作用:第三章概述了數字同步網技術,著重描述了同步網的基本概念,分析了建立同步網的必要性,講述了各種同步方法;第四章闡述了同步定的傳輸;第五章介紹了bits設備所支持的同步狀態消息;第六章、第七章為本文的重點,通過對建立數學模型,從理論上分析內部噪聲和相位瞬變產生損傷的原理,企圖尋找到更好地頻率漂移的方法。
  10. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求,課題期間研製了下位機系統硬體和軟體,開發了上位機監軟體,其中所作的具體工作包括:測量原理的研究和在系統中的實現,在本次設計中用三種方法來進行水位測量,分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法;主晶元的選擇,我們選用了高集成度的混合系統級晶元c8051f021 ;實現了的採集和處理,包括的轉換和在單片機內的運算;高集成度16位模數轉換晶元ad7705在系統中的應用,我們完成了它與單片機的介面設計及程序編任務;精確晶元ds1302在系統中的應用,在此,我們實現了用單片機的i o口與ds1302的連接和在軟體中對序的模擬,該晶元的應用給整臺儀器提供了間基準,方便了儀器的使用;另外,針對研製任務的要求,還給系統加上了一路4 20ma模擬電流環的輸出電路來提供系統監測,該部分的實現是通過採用ad421晶元來完成的,本設計中完成了ad421與單片機的spi介面任務,協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系,並完成了程序設計;與上位機的通介面設計,該部分通過兩種方法實現: rs232通方式和rs485通方式;系統設計方面還包括報警電路設計、操作鍵盤設計、電源監電路設計、電壓基準電路的設計。
  11. Pcb board is finished by using protell99se. power supply module, signal - sampling module, mcu, keyboard input, lcd module, and cpld are designed. the third chapter completes the software design and the debugging in keil environment

    然後利用protell99se平臺完成pcb圖的設計和板工作,根據晶元資料設計出供電模塊,採集模塊,單片機系統,日歷晶元,鍵盤輸入,液晶顯示系統,可編程式模塊和各個模塊間介面。
  12. Clock control signal

    時鐘控制信號
  13. The clock control da chip of mb40978 converts rgb digital vedio singal into amplitude - modulated rgb pulse that is magnified and inner - modulate laser

    經過處理的rgb視頻數字經過的da轉換和一級驅動,產生調幅脈沖,實現半導體激光器的內調
  14. The signal collecting system of singlechip collects the signals from generator. the paper introduces the every part of the singlechip. the key component is a 8051cpu, its surrounding circuits include dc power source, simulating signal collecting circuit, digital signal collecting circuit, a / d converting circuit, clock generating circuit, counting frequency circuit, controlling circuit, communicating circuit, and some other circuits

    前臺單片機採集系統完成對發電機組多息量的採集,本文詳細介紹了電路設計,系統的核心器件為8051cpu ,其外圍電路包括電源電路、模擬採集電路、 a d轉換電路、數字採集電路、發生電路、測頻電路、電路、通訊電路等。
  15. In the time - domain, based on the principle of random sampling of dso. two way ( " time amplifing in dual slope integral " and " time - voltage convert " ) are implemented to measure the time between the system triger and writing clock. thus random sampling interpolate can be done to measure repeated signal in high frequency with the a / d convert and controller which frequency are lower

    域,根據數字示波器隨機取樣原理,用兩種方法(雙斜率積分間放大測量方法和間? ?電壓轉換測量方法)測量數字示波器系統觸發和采樣寫間間隔,用低速a / d轉換器及器進行模?數轉換和,以此進行隨機取樣內插,從而實現了對高頻率重復的測量。
  16. In its digital processing circuit, clock chip with high precision and temperature compensation is uesd as reference clock. high frequency reversible counter is used to count trimmed impulse signal forward or backward and two pathes saw signals are selected timely by multichannel selector

    數字處理電路採用高精度、具有溫度補償的晶元作為基準,採用高頻可逆計數器對整形后的脈沖進行正向或逆向計數,採用高性能的多路選擇器兩路saw的定選擇。
  17. System control module accomplishes many functions, such as systemic initialization, controling work of the system, man - machine interface and selecting channel. it communicates with other modules by i2c bus. timing signals are inputed into microprocessor through p1 port and control signals are provided through p2 port

    系統模塊和其他模塊間的通訊基於i ~ 2c總線,並利用了p1口進行各的檢測和利用p2口的各線作為線宋相應模塊的工作。
  18. Again, the keyboard / mouse always generates the clock signal, but the host always has ultimate control over communication

    重復一遍,鍵盤/鼠標總是生成,而主機著整個通過程。
  19. At the base of earnestly analysis to the ov7620 working sequence, using its frame synchronization, field synchronization and the pixel - clock signal, completed gathering of the active power meter reading image which is reduced resolutions at the control of mcu

    在仔細分析ov7620工作序的基礎上,利用其幀同步、場同步和像素,在單片機的下完成了對電度表讀數圖像的降低解析度採集。
  20. The clock and data pulsation signals from upper sensor heads can be received using pin diode, then, amplified and inverted in logical control unit for the purpose of cpu operation. hereinafter, the digital signal will be delivered into the central processing unit ( cpu ) for related calculation, and meanwhile transmitted to a d / a converter for signal recovery after filter and phase - shift circuit

    通過採用pin管接收從傳感頭傳遞下來的脈沖和數據脈沖,並將它們放大整形傳送到邏輯單元,產生邏輯,再將數字傳送給d / a轉換器,設計了濾波器和移相器電路,還原出了原始的被采樣
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