時鐘放大器 的英文怎麼說

中文拼音 [shízhōngfàngdàqì]
時鐘放大器 英文
clock amplifier
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 放 : releaseset freelet go
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 放大器 : amplifier; pantograph; lawnmower; enlarger; magnifier
  • 放大 : amplify; magnify; boost; enlarge; blow up; gain; amplification; enhancement; multiplication; magn...
  1. Using domestic strained integrated resistor as weighing sensor, at89c52 single chip as control unit, combined with arithmetical magnification, analogtodigital conversion ( a / d ), real time clock, liquid crystal display ( lcd ), and series communication interface, a minitype automatic weighing lysimeter is developed. that made measurement of evapotranspiration become conveniently and effectively in studying on water use of crops

    為了方便、有效地測定植物的蒸散，為水分利用研究提供價廉物美、簡單易用的儀器，本研究利用國產的集成電阻應變式稱重傳感器，採用at89c52單片機作為控制單元，結合運算放大、模數轉換、實時時鐘、液晶顯示、數據存儲、串列通信等外圍介面電路，研製了小型自動稱重式蒸散儀。
  2. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  3. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  4. One of the most promising new technologies to help achieve that goal is a new breed of low - powered microprocessors that can vary the speeds at which they operate

    在執行復雜的計算任務，如連續處理大批的數字數據時，這種處理器以極高的速度，即"時鐘脈沖速度"運行。但是在執行要求較低的任務，如運行一個文字處理器或放音樂時，該晶元能減速。
  5. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  6. The paper first reviews the research background and actuality of the filter " s design in china and other country, introduces the meaning of the project and the work of the paper, narrates the theory of the switched - capacitor network and the basic switch building blocks, analyses the related factors of the design of sc filter. such as the selection of the architecture, the trade off of the opamp " s gain, bandwidth, phase margin, slew rate and setting time, the effect of the switch " s on resistor, how to reduce the charge injection and the clock feed - through, the power consumption and the selection of the sampling frequency and so on

    本文首先回顧了濾波器設計的國內外研究背景和現狀，介紹了本課題提出的意義以及本文的主要工作，論述了開關電容網路原理和基本開關模塊，分析了開關電容濾波器設計的相關因素：電路結構的選擇，對運算放大器設計中高增益、寬帶寬、相位裕度、轉換斜率和建立時間等的折中考慮，開關的打開電阻對電路的影響，開關電容電路中怎樣減少電荷注入和時鐘饋通，以及整個電路的功耗問題和采樣頻率的選擇等。
  7. The adm system mainly includes a oscillator, a clock generator, an amplifier, a pre - amplif ier, a comparator, an agc ( automatic gain control ), an adm analyzer & synthesizer, a d / a converter and a lowpass filter

    整個系統包括：內置振蕩器，時鐘產生器，放大器，前置運算放大器，比較器， agc （自動增益控制器） ， adm分析綜合器，數模轉換器以及低通濾波器。
  8. In the time - domain, based on the principle of random sampling of dso. two way ( " time amplifing in dual slope integral " and " time - voltage convert " ) are implemented to measure the time between the system triger and writing clock. thus random sampling interpolate can be done to measure repeated signal in high frequency with the a / d convert and controller which frequency are lower

    在時域，根據數字示波器隨機取樣原理，用兩種方法（雙斜率積分時間放大測量方法和時間? ?電壓轉換測量方法）測量數字示波器系統觸發和采樣寫時鐘間時間間隔，用低速a / d轉換器及控制器進行模?數轉換和控制，以此進行隨機取樣內插，從而實現了對高頻率重復信號的測量。
  9. Input to the inverting oscillator amplifier and input to the internal clock operating circuit

    反向振蕩放大器和內部時鐘工作電路的輸入。
  10. And the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed combined with the characteristics of the modulator architecture. based on it, the switched - capacitor integrator, class a amplifier, nonoverlap clock, voltage reference, comparator, feedback dac have been designed. in the end, the layout design is shown

    調制器採用全差分開關電容電路實現，並根據系統結構特點就如何優化電路結構、克服電路中存在的非理想特性、提高電路性能作了具體分析，在此基礎上完成了開關電容積分器（開關、電容、運算放大器） 、參考電壓源、比較器、兩相非交疊時鐘、反饋dac等模塊的電路結構和參數設計。
  11. The familiar " ding - ding " sound you heard at the beginning of the ceremony comes from a foot bell, and the device displayed here should be recognizable without close scrutiny as the traditional tram controller, commonly called " gongdoulah " in punti dialect. they are not only the icons of hong kong trams, which fill us with poignant and powerful nostalgia, but also distillations of the city s development over the years

    大家可能對剛才儀式開始時的聲響有點熟悉，對臺上擺放的儀器亦有點印象。它就是沿著港島電車路不時傳來「叮叮」聲的「腳鐘」和俗稱「干都拿」的電車控制器。
  12. In fact, it is more effective in system level. low power technique of microprocessor is composed of clock - gating, close part of cache, and dvs ( dynamic voltage scaling ). low power technique of peripheral equipments design is composed of closing the idle parts of the equipment and degrading the service quality satisfied with lowest requirement

    處理器的低功耗設計大都採用系統級，其技術主要包括:門控時鐘技術， cache部分關閉技術，動態電壓縮放dvs （ dynamicvoltagescaling ）技術;外圍設備低功耗設計包括:關閉設備空閑部件;在滿足基本性能要求前提下，降低外圍設備的服務質量。
  13. The radio frequency receiver supports interface for instrument and base station and air interface for mobile station, and it takes the task of magnifying low noise and down - convert and digital baseband processor filtering and magnifying intermediate frequency to reverse link signal. the digital baseband processor samples the received signal after down - convert radio frequency signal to intermediate frequency signal and processes other processing and supports interfaces to computer, next sends data to computer. the gps receiver supports interface for instrument and gps system, and receives gps system signal, next it demodulates the correlative information and sends out benchmark clock signal we need

    射頻接收部分主要為儀器和基站、移動臺提供空中介面，其主要任務是在反向鏈路上對接收到的射頻調制信號進行低噪聲放大、射頻下變頻變換、中頻濾波放大等;數字基帶部分為對接收信號變頻為中頻后進行a / d采樣，以及其他的rsp處理並和計算機提供介面，將數據送至計算機進行后臺處理、顯示等; gps接收機部分為儀器和gps系統提供介面，接收gps系統信號並解調相關信息，輸出所需的電文及時鐘基準信息等。
  14. The clock and data pulsation signals from upper sensor heads can be received using pin diode, then, amplified and inverted in logical control unit for the purpose of cpu operation. hereinafter, the digital signal will be delivered into the central processing unit ( cpu ) for related calculation, and meanwhile transmitted to a d / a converter for signal recovery after filter and phase - shift circuit

    通過採用pin管接收從傳感頭傳遞下來的時鐘脈沖和數據脈沖信號，並將它們放大整形傳送到邏輯控制單元，產生邏輯控制信號，再將數字信號傳送給d / a轉換器，設計了濾波器和移相器電路，還原出了原始的被采樣信號。
  15. Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology

    然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
分享友人
分享到 Line

分享到臉書