時鐘相位 的英文怎麼說

中文拼音 [shízhōngxiāngwèi]
時鐘相位 英文
clock phase
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 相 : 相Ⅰ名詞1 （相貌; 外貌） looks; appearance 2 （坐、立等的姿態） bearing; posture 3 [物理學] （相位...
  • 位 : Ⅰ名詞1 （所在或所佔的地方） place; location 2 （職位; 地位） position; post; status 3 （特指皇帝...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 相位 : phase position; phase
  1. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  2. Thirdly, the paper discusses the driver of the peripheral equipment, how to port the uc / os - n and uclinux, h. 323 protocol and the application of the system in the digital speech classroom. also some software and hardware measure are adopted to enhance the system stability. at last, the shortcoming and the something to be improved are given. dsp can be used to realize real - time speech coding algorithm, and after porting ( ac / os - n, arm can manage the keyboard, the lcd and the ethernet peripheral etc. then the embedded network system with specific purpose can be used in others fields, such as pda, set of top, web tv, ect

    在實際設計實現中，為提高系統軟、硬體整體穩定性和可靠性，使用了以下幾種方法： （ 1 ）低電壓復位、抗電源抖動能力、增加時鐘監測電路、抗電磁干擾能力、散熱等技術； （ 2 ）多層pcb設計，線路板結構緊湊，電源部分採用數字5v 、 3 . 3v 、 3v 、 1 . 8v和模擬5v多電源供電； （ 3 ）選用表面貼和bga封裝的器件； （ 4 ）按照軟體工程的要求進行系統分析，規劃系統框圖、流程分析、模塊劃分，減小了不同模塊的相關性，從而最大限度避免了錯誤的發生。
  3. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法，重點介紹了視頻信號數字化技術、抗混疊濾波器、箝位、增益控制、鎖相技術、同步時鐘產生、電視信號亮色分離、彩色解碼等技術，這些關鍵技術為視頻信號的數字化處理提供了重要的基礎。
  4. In this paper, a clock recovery system that based on phase control technology is studied

    本文設計的鎖相環路是基於相位控制技術的時鐘恢復系統。
  5. Then we turned in the input laser to observe the decline of phase conjugate reflectivity. measuring dark storage time, we found that the phase conjugate reflectivity declined to 50 % of steady - state value when photorefractive crystal was in dark condition for 30 minutes. even after 9 hours, there still existed remaining reflectivity, which could n ' t be measured by our detector

    因而研究了晶體內位相共軛光柵存儲特性，即觀察位相共軛光柵形成后在黑暗條件下能存儲的時間，實驗結果得出位相共軛光柵在黑暗中30分鐘后，位相共軛反射率下降到原來的50 ，而在黑暗中9小時后，位相共軛光非常微弱，無法測出。
  6. Gps is a planet wireless conductance system which is global and all - weather, gps can offer high precision time orientation information to infinite user, clock precision reachs 10 ? 6 magnitude 。 not only changes traditional time method of quartz crystal clock, but also replaces wireless shortwave and even more lowfrequency signal and tv signal whose overlay range is limited and low precision, offers advantage to geology field task, achieve automatization and high precision of seismic flow observation

    利用gps授時信號全方位、全天候、連續性、實時性和高精度的特點，以gps信號為基準來校準本地時鐘（晶體振蕩時鐘或原子鐘） ，將gps接收機輸出信號的長期穩定度和恆溫晶振的短期穩定度相結合，應用大規模可編程邏輯器件，設計和實現了由pc104控制的實時在線授時系統。
  7. Fist, quick bit synchronization. the common methods are relative synchronization, multi - phase clock sample and so on

    第一，快速比特同步。常規的方案有相關同步法和多相位時鐘采樣法等。
  8. The paper first reviews the research background and actuality of the filter " s design in china and other country, introduces the meaning of the project and the work of the paper, narrates the theory of the switched - capacitor network and the basic switch building blocks, analyses the related factors of the design of sc filter. such as the selection of the architecture, the trade off of the opamp " s gain, bandwidth, phase margin, slew rate and setting time, the effect of the switch " s on resistor, how to reduce the charge injection and the clock feed - through, the power consumption and the selection of the sampling frequency and so on

    本文首先回顧了濾波器設計的國內外研究背景和現狀，介紹了本課題提出的意義以及本文的主要工作，論述了開關電容網路原理和基本開關模塊，分析了開關電容濾波器設計的相關因素：電路結構的選擇，對運算放大器設計中高增益、寬帶寬、相位裕度、轉換斜率和建立時間等的折中考慮，開關的打開電阻對電路的影響，開關電容電路中怎樣減少電荷注入和時鐘饋通，以及整個電路的功耗問題和采樣頻率的選擇等。
  9. Bits supplies the synchronous timing signal to these equipments inside the telecommunicationt building, such as dps, atm, no. 7, dxc, tm & adm in sdh, don and in etc. the related techniques are involved in the content of synchronization ne twork, timing distribution, the timing signal transportations x impairments etc. the second chapter tells the structure and the function of the building integrated timing system. the third chapter summarizes the digital synchronization network techniques, which emphasizes the basic concept of synchronization networks analyzes the necessity of building the synchronization network and introduces all kinds of synchronization methods. the fourth chapter represents the transportation of the synchronization signal

    本文第二章講述了通信樓綜合定時系統的構成及作用：第三章概述了數字同步網技術，著重描述了同步網的基本概念，分析了建立同步網的必要性，講述了各種同步方法；第四章闡述了同步定時信號的傳輸；第五章介紹了bits設備所支持的同步狀態消息；第六章、第七章為本文的重點，通過對時鐘信號建立數學模型，從理論上分析時鐘內部噪聲和相位瞬變產生時鐘定時信號損傷的原理，企圖尋找到更好地控制頻率漂移的方法。
  10. Parallel structure of poly - phase decomposition and parallel mixer is applied in the ddc circuit, it solves the bottleneck in mixing and increases the handle speed. the partition of the tuning channel according to the digital mixing sequence, and the ddc by means of decimating first, the low - pass filtering and mixing realize efficiently the down - conversion of the variable carrier frequency band - pass signal. according to the structure of the ddc and the requirement of the frequency

    短數據快速測頻演算法的具體實現:使用并行流水線的設計方法，提高了系統的數據吞吐率，在100mhz的系統時鐘下，能夠實時處理400mhz ~ 600mhz速率a / d采樣的數據，在64點采樣， 100mhz系統時鐘情況下，初次測頻佔用時間640ns ，以後每次測頻佔用時間縮短到160ns ，實時地提供多相濾波下變頻所需的載頻位置信息，縮短了接收機的調諧時間。
  11. Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains. the data transaction protocol comes from the most basic work way of uart. when the master clock is 16. 7mhz, the pcm side and adpcm side clocks both are 2. 38mhz, the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14. 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14. 7 us

    在主時鐘為16 . 7mhz ， pcm數據端與adpcm數據端時鐘均為2 . 38mhz時，模擬結果表明從pcm的起始位輸入uart接收器到adpcm終止位輸出uart發送器的最大延遲為14 . 3 s ，從adpcm的起始位輸入uart的接收器到pcm終止位輸出uart發送器的最大延遲為14 . 7 s ，設計時盡可能的使編碼與解碼的時間相差不多，從結果看出基本達到這個要求。
  12. The paper compares some algorithms on rs decoding, makes improvements based on the me algorithm, removes the modifying step in decoding truncate rs code, corrects unsuitable statements in the related papers, and parameterizes the rs decoding module, reducing its area by 20 %. the paper overcomes the signal integration problem in multi - clock design, greatly lowers the phase jitter without area increase, introduces pll to adjust rate for the first time, and parameterizes the module

    本文比較了實現rs解碼的幾種演算法，並在me演算法基礎上進行改進，創造性的去掉了縮短碼解碼中的校正環節，糾正了有關論文中的不當論述，並將rs解碼模塊進行了參數化設計，同時也將rs解碼的規模縮小了20 ；克服了多時鐘設計中的信號完整性難題，在沒有增加模塊面積的條件下，大幅降低數據的相位摘要抖動，首次引入鎖相環來調整速率。
  13. The 33220a external frequency reference lets you synchronize to an external 10 mhz clock, to another 33220a, or to an agilent 33250a. phase adjustments can be made from the front panel or via a computer

    33220a外部頻率基準使您能同步于外部10mhz時鐘另一臺33220a ，或agilent33250a .相位調整可從前面板或通過
  14. Therefore, a four - phase charge pump circuit is invented to surmount this problem, but the current loading capability of this circuit is unfavorable and the driving clocks must have four - phase non - overlapped " signals

    針對這個問題，四相位的電荷泵電路由此產生，但是這個電路的電流負載能力不太好並且它的驅動時鐘信號必須是四相位且不重疊。
  15. The adc aperture jitter must be minimal, and the sampling clock generated from a low phase - noise quartz crystal oscillator

    Adc的孔徑抖動必需盡可能的小，而且要使用低相位噪聲的石英晶體振蕩器作為采樣時鐘發生器。
  16. Aiming at the scheme of the signal electromagnetic environment simulator of the wireless communication system, the mission of this project is to design and realize twenty - four frequency synthesizers, which must meet high expectation for the phase noise characteristic and the spurious repression characteristic of the output clock signal. these frequency synthesizers provide the moving of the basic signal generating modules to radio frequency with stable inspiring source

    本課題的任務是針對通信信號電磁環境模擬器系統的方案要求，設計實現24個（頻率分佈在260mhz 1430mhz之間）對輸出時鐘信號的相位噪聲特性、雜散抑制特性等要求都很高的頻率合成器，為基本信號生成模塊到射頻的搬移提供穩定可靠的激勵源。
  17. Chapter 4 proposes 2 algorithms which pointed to digital lcos and analog lcos, compared with other algorithems that have published, this 2 algorithm can achieve 8, 64, 4096 colors and 24bit true color, which means they have very good color adaptability. the clock computing after that mapped the 2 algorithms into the clock definition level of fpga, which means good engineering implementation. the clocks computing here are based on the 2 algorithms, and these establishes foundation for the rest analyse & design works

    第四章在前人工作的基礎上提出了針對數字式lcos和模擬式lcos像源的2種fsc演算法，相對于其它公開發表的演算法來說，這2種演算法可實現8色、 64色、 4096色、 24位真彩色等不同色彩數下的fsc顯示，具有更好的色彩適應性，且隨后的時鐘計算將這2種演算法映射到fpga內的時鐘定義層次，具有更好的可執行性和工程實踐性。
  18. An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,

    提出設計了usb介面電路的整體構架，設計了usb的主要控制邏輯和與mcu的互連的介面（此介面與飛利普的usb介面晶元pdiusbd12兼容） ，也設計了一個數字鎖相環（ dpll ）來同步數據和分離時鐘，並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
  19. Their inner clocks tell them just where the sun will be and they change their course correspondingly

    它們體內的時鐘告訴他們太陽應在的位置，據此它們相應地改變前進的方向。
  20. Although ranging is adopted, certain phase shifts still exist between bit flows from onus to olts. therefore, fast synchronization must be applied to synchronize the receiving clock of olt to the bit flow being received from a certain onu

    雖然採用了測距技術，但是各onu到達olt處的比特流仍存在一定的相位漂移，所以必須採取快速同步的技術，將olt的接收時鐘同步到當前所接收的、來自某一onu的比特流。
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