時鐘線路 的英文怎麼說

中文拼音 [shízhōngxiànlù]
時鐘線路 英文
clock circuit
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 線路 : 1. [電學] circuit; line 2. [交通運輸] line; route
  1. The clock circuitry has also been built into the 8085.

    時鐘線路也裝入了8085中。
  2. Going in the other direction, an intel p4 or amd athlon running at clock speeds over a gigahertz should be able to satisfy the requirements of a 45 megabit t3 line

    另一方面，以超過1ghz的時鐘速度運行的intel p4或amd athlon應該能夠滿足一條45兆位t3線路的需求。
  3. Thirdly, the paper discusses the driver of the peripheral equipment, how to port the uc / os - n and uclinux, h. 323 protocol and the application of the system in the digital speech classroom. also some software and hardware measure are adopted to enhance the system stability. at last, the shortcoming and the something to be improved are given. dsp can be used to realize real - time speech coding algorithm, and after porting ( ac / os - n, arm can manage the keyboard, the lcd and the ethernet peripheral etc. then the embedded network system with specific purpose can be used in others fields, such as pda, set of top, web tv, ect

    在實際設計實現中，為提高系統軟、硬體整體穩定性和可靠性，使用了以下幾種方法： （ 1 ）低電壓復位、抗電源抖動能力、增加時鐘監測電路、抗電磁干擾能力、散熱等技術； （ 2 ）多層pcb設計，線路板結構緊湊，電源部分採用數字5v 、 3 . 3v 、 3v 、 1 . 8v和模擬5v多電源供電； （ 3 ）選用表面貼和bga封裝的器件； （ 4 ）按照軟體工程的要求進行系統分析，規劃系統框圖、流程分析、模塊劃分，減小了不同模塊的相關性，從而最大限度避免了錯誤的發生。
  4. Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently

    文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小
  5. High - qualified designers and engineers of chaowei are able to provide various high - qualified design services such as ic software program, circuit board, product appearance, products structure, and product package, etc. the factories directly under chaowei have advanced production abilities including mould making, inection moulding, surface spray - painting, silk - screening, shift - screening, smt, welding and assembling, quartz clock core production, and quality check and assurance. chaowei held many design patents and utility model patents, at the same time, national clock and watch quality certification, national technical supervision bureau certification, usa fcc and astm security authentication, canada ic, and euro ce are achieved, the rich experience in oem and odm can ensure high quality products and professional service

    超維公司擁有一批高素質的專業設計師和工程師，有能力為國內外客戶提供包括ic軟體編程線路板設計產品外觀設計產品結構設計產品包裝設計等多方面高水準的設計服務超維的直屬工廠則擁有模具製造注塑成型表面噴漆絲印移印smt焊接裝配石英鐘機芯製造品質檢驗測試等先進的生產能力超維公司的產品擁有大量的外觀設計專利和實用新型專利，同時獲得了國家鐘表質量檢驗中心的合格證書國家技術監督局檢驗合格證書美國fcc認證和astm安全認證加拿大ic認證歐盟ce認證。
  6. The precise clock source is crystal oscillator made of 74hc04 ; the mute circuit can conceal the error and solve the problem of noise ; the antenna switching circuit in the receiver is to select one antenna from two which receives signal better. it can improve the quality of the receiving audio signal, restrain the noise effectively and promote the system performance

    高精度的時鐘源是由74hc04構成的晶體振蕩器;靜音電路將出錯的音頻信號進行差錯掩蓋，很好地解決了噪聲問題;接收機採用兩副天線切換工作，提高了音頻信號接收質量，有效地抑制干擾，提升了系統的性能。
  7. The data and clock lines are both open collector

    數據和時鐘線都是集電極開路的。
  8. Over the transfer network, which serves as a common transfer platform for different telecommunications services, the growth of services, including voice, data, multimedia, leased lines and broadband service, and the development of the support networks such as the signaling network, the clock transfer network and the nm liaison network have made demand for transmission circuits

    傳送網作為各種電信業務的公共傳送平臺，包括話音、數據和多媒體、專線、寬帶業務等在內的各類業務的增長，以及信令、時鐘傳送、網管聯絡等支撐網的增長，均對傳輸電路提出需求。
  9. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  10. China recently agreed to straighten a route for airlines crossing its airspace which has cut 15 minutes off a flight to europe

    中國最近同意為飛越其領空的飛機把一條線路改為直航線，這給前往歐洲的航班節約了15分鐘的時間。
  11. The capacitor has advantages of low dissipation, high insulation resistance, good self - healing character, and steady electricity performance, anti - striking current, strong over - carrying capacity, etc. it is assembled sith inner hidden discharge resistance. it is applied in high or low pressure sodium lamp and mercury - arc lamp for the help of power factor compensation

    斷開電流允許時間：在0 . 5秒內的8個半周波前跳閘絕緣電壓ul1699第59節：線路與負載之間1000v ， 1分鐘
  12. Auto power cut - off when standby for 30 minutes or temperature test system failure. it achieves energy save, safety and prolongs life of heater

    當30分鐘閑置，或測溫系統出現故障，如焊咀溫度低於警誡線，發熱芯或線路板發生故障時，自動切斷電源，具安全，省電及延長芯頭壽命的優勢。
  13. With vc - 12 virtual concatenation, we can make efficient and flexible use of the bandwidth. sdram, as a mass storage medium, is applied also. in this design, i use hy57v643220ct - 6, with 32bit data width, up to 166m system clock, as the buffer of vc - 12 virtual concatenation alignment and ethernet data transmission

    本論文設計系統中採用了現代的hy57v643220ct - 6作為外部存儲器，它的數據線是32位寬，保證了吞吐量，時鐘可高達166m ，保證了速度，用它實現了多個以太網發送端緩存和多路vc - 12虛級聯的對齊。
  14. 10 the single journey time on a bus route is 25 mins, and 5 mins is allowed in the schedule before the next journey to recover from any late running

    巴士完成一次線路所用時間為25分鐘，在下一班出發前允許有5分鐘的時間以彌補可能的延誤。
  15. The periphery electric circuit of adc was designed, including 3 - wire serial port configuration circuit, analog input electric circuit, clock input circuit and power

    對adc的外圍電路進行設計，包括三線串口配置電路、模擬輸入電路、時鐘輸入電路和電源電路。
  16. Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment

    Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。
  17. The surrounding circuits design mainly includes the clock circuit, mute circuit and antenna switching circuit

    其中外圍電路涉及到時鐘電路、靜音電路和天線切換電路的設計。
  18. Just then, the two brothers in charge of technical arrangements whispered excitedly at my side, were about to make the connection. please ask master to give us another minute

    就在此時，負責技術方面的兩位師兄在旁邊小聲又興奮地對我說：線路就要接通了，請師父再等一分鐘。
  19. In order to improve reliability and simplify the hardware design, many new i2c bus elements were used to realize binary input, logic output, clock functions and storing settings and reports. by simulating i2c bus data transfer, the mcu realized writing and reading data from each element the whole hardware system ' s structure is compact and reasonable, and the device has high reliability, stability and immunity to disturbance

    從提高可靠性和簡化電路的角度出發，設計硬體電路板時使用了許多新型i ~ 2c串列介面器件， mcu用普通i / o口模擬i ~ 2c總線介面，由軟體模擬i ~ 2c總線數據傳輸過程，實現了開入開出、定值存儲、報告存儲和時鐘對時等功能。
  20. It includes the design of trigger circuit, high speed clock circuit, a / d digital and data acquisition circuit, time inter - plug circuit and pci interface circuit 。 3. the function debug of hardware and the result analysis

    主要包括觸發電路的設計、高速時鐘電路設計、 a / d數字化與數據採集電路設計、時間內插電路設計和pci總線介面設計。 3 .硬體功能調試及其結果分析。
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