時鐘負載 的英文怎麼說

中文拼音 [shízhōngfùzǎi]
時鐘負載 英文
clock load
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 負 : Ⅰ名詞1 （負擔） burden; load 2 （虧損） loss 3 （失敗） defeat Ⅱ動詞1 [書面語] （背） carry on th...
  • 載 : 載Ⅰ名詞（年） year : 一年半載 six to twelve months; six months to a year; 三年五載 three to five ...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 負載 : [電學] load
  1. Some typical machine attributes include the amount of memory, cpu type, cpu clock speed, and current machine load

    典型的機器屬性包括內存數量、 cpu類型、 cpu時鐘速度以及當前的機器負載。
  2. An optimized method of clock - tree is introduced. the whole length of the clock - tree is reduced by decrease the load of new node, the performance of clock - tree is improved

    摘要介紹了一種新的時鐘樹優化策略。通過減小時鐘樹子節點的負載，從而減少整時鐘樹線長，使時鐘樹性能得到了提高。
  3. The mains are monitored by automatic control system. generator set will take over and supply power to the load within max. 15 seconds when the mains supply fail

    自動監測系統常年監測主電網供電。當主電網突發停電時，發電機組將在15秒鐘內自動完成從發電機組起動到向負載送電。
  4. Two or more generators shall be used to generate electricity by the synchronous equipment

    發電機在帶負載試運時，每隔30分鐘記錄一次相電流、繞組和軸承溫度。
  5. The capacitor has advantages of low dissipation, high insulation resistance, good self - healing character, and steady electricity performance, anti - striking current, strong over - carrying capacity, etc. it is assembled sith inner hidden discharge resistance. it is applied in high or low pressure sodium lamp and mercury - arc lamp for the help of power factor compensation

    斷開電流允許時間：在0 . 5秒內的8個半周波前跳閘絕緣電壓ul1699第59節：線路與負載之間1000v ， 1分鐘
  6. Today, there are grid schedulers, resource managers, and workload management systems available that can provide the functionality of the traditional batch queuing system or provide the ability to harness cycles from idle desktop workstations

    現在，有一些網格調度器、資源管理器和任務負載管理系統可以提供傳統的批處理隊列系統的功能，或者提供從空閑桌面工作站中利用時鐘周期的能力。
  7. Therefore, a four - phase charge pump circuit is invented to surmount this problem, but the current loading capability of this circuit is unfavorable and the driving clocks must have four - phase non - overlapped " signals

    針對這個問題，四相位的電荷泵電路由此產生，但是這個電路的電流負載能力不太好並且它的驅動時鐘信號必須是四相位且不重疊。
  8. First, we propose a topology generation method to generate the clock tree topology with minimal output net loading

    首先，我們提出一個時鐘樹拓樸生成方法來產生擁有最小輸出負載的時鐘樹拓樸。
  9. Some typical machine attributes include the amount of memory, the cpu type, the cpu clock speed, and current load

    典型的機器屬性包括內存總量、 cpu類型、 cpu時鐘速度以及當前的負載。
  10. Process management and scheduling, inter - process communication, storage management, parallel control, file systems, transaction, clock synchronization, security mechanism, etc. the research topic of this thesis is " load distribution ", a destination of distributed process management and scheduling

    分散式操作系統涉及到多個方面的工作，如：進程管理和調度、進程間通信、存儲管理、並發控制、文件系統、事務處理、時鐘同步、安全機制等。本論文的研究范圍是針對分散式進程管理和調度的目標之一： 「負載分佈」 。
  11. The switch power will operate at ccm condition when circuit is set to pwm mode. when pfm mode is selected for the operation mode, the switch power will still operate at pwm condition with the high load, the system will cancel the pwm mode and enter the pfm mode only when the load is drop to a certain threshold to boost the operation efficiency at light load, make the ic has high efficiency within wide load range

    選擇pwm模式，開關電源將工作在ccm模式下;選擇pfm模式，在負載較高的情況下，開關電源仍然工作于pwm模式，只有當負載降低到一定程度時，開關電源才退出pwm模式，而按照pfm工作模式操作，跨過一部分時鐘周期，降低頻率相關功耗，以提高輕負載時低效率的問題，使得開關電源在很寬的負載范圍內都具有高效率。
  12. In this paper, low power flip - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed

    與此相對應的，在本論文中，分別對將少時鐘負載或數據通路的負載的觸發器設計；減小時鐘信號幅度的觸發器設計；降低時鐘頻率的雙邊沿觸發器設計以及應用門控技術來減少觸發器無效跳變設計的觸發器結構進行了討論。
  13. To 2 minutes in order to smoke test your load test

    將「運行持續時間」設置為2分鐘，以便對負載測試執行冒煙測試。
  14. Dynamic power is dominant component of the average power dissipation in cmos circuits. and the value of dynamic power is determined by node capacitance, supply voltage, clock frequency and switching activity of cmos circuits. so most low power designs are achieved by reducing one or more those above parameters

    由於cmos電路的功耗與cmos電路的負載電容，電壓，時鐘頻率及開關活動性有關，因此在低功耗cmos觸發器設計過程中，許多低功耗設計技術都可以歸結到通過減小上面的參數來達到低功耗的目的。
  15. In all cases, load on the server was such that response times never exceeded one second, and were generally much less the heaviest user test with 2 gb mail files and everything in the inbox had response times of 750 msec ; the lightest users had 11 msec response times

    在所有的情況下，服務器端的負載都是這樣的，響應時間從未超過一秒鐘，通常會更短（用2 gb的郵件文件和收件箱中的所有郵件進行測試，負載最大的用戶響應時間為750 msec ；負載最小的用戶響應時間為11 msce ） 。
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