時鐘輸出 的英文怎麼說

中文拼音 [shízhōngshūchū]
時鐘輸出 英文
clock out
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 輸 : Ⅰ動詞1 （運輸; 運送） transport; convey 2 [書面語] （捐獻） contribute money; donate 3 （失敗） l...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 輸出 : 1 （從內部送到外部） export 2 [電學] output; outcome; outlet; out fan; fanout; 輸出變壓器 output ...
  1. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  2. The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse.

    每當計數器被時鐘脈沖觸發一次時，計數器輸出的二進制數便累減1。
  3. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  4. Chapter 3 treats the algorithm implementation of demodulator in the receiving asic of dvb - s. in detail, demodulation includes carrier recovery and symbol synchronization. together with the transmission characterization of band - limited input signals the chapter proposes a scheme for implementing carrier recovery loop

    解調具體分為載波恢復、時鐘同步兩大部分，本章著重論述了載波恢復的原理並結合dvb - s輸入信號傳輸特性，提出了相應的實現方案，對部分電路進行了性能分析。
  5. Gps is a planet wireless conductance system which is global and all - weather, gps can offer high precision time orientation information to infinite user, clock precision reachs 10 ? 6 magnitude 。 not only changes traditional time method of quartz crystal clock, but also replaces wireless shortwave and even more lowfrequency signal and tv signal whose overlay range is limited and low precision, offers advantage to geology field task, achieve automatization and high precision of seismic flow observation

    利用gps授時信號全方位、全天候、連續性、實時性和高精度的特點，以gps信號為基準來校準本地時鐘（晶體振蕩時鐘或原子鐘） ，將gps接收機輸出信號的長期穩定度和恆溫晶振的短期穩定度相結合，應用大規模可編程邏輯器件，設計和實現了由pc104控制的實時在線授時系統。
  6. The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse

    每當計數器被時鐘脈沖觸發一次時，計數器輸出的二進制數便累減1 。
  7. If all errors belong to single or multiple temporary 0 1 - error or stuck - at - error produced by one module, then these errors can be corrected effectively. the results obtained from the simulation validate the correctness of the cl - acl structure. analytic results show that the delay of the cl - acl structure is dramatically less than that of a dmr structure using alternating - complementary logic mode

    這些粒子所引起的干擾不僅將改變存儲單元的邏輯值，而且將導致邏輯電路產生瞬時輸出脈沖，如果這些脈沖在某個關鍵的時間段里產生，比如在時鐘或數據的變化過程中，那麼它們將間接地使其它電路的狀態產生變化。
  8. The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions

    本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。
  9. High - speed printers can print an entire line at one time, turning out as many as 20 000lines a minute

    高速印表機能同時列印一整行，一分鐘能輸出20000行。
  10. Over the transfer network, which serves as a common transfer platform for different telecommunications services, the growth of services, including voice, data, multimedia, leased lines and broadband service, and the development of the support networks such as the signaling network, the clock transfer network and the nm liaison network have made demand for transmission circuits

    傳送網作為各種電信業務的公共傳送平臺，包括話音、數據和多媒體、專線、寬帶業務等在內的各類業務的增長，以及信令、時鐘傳送、網管聯絡等支撐網的增長，均對傳輸電路提出需求。
  11. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  12. Pcb board is finished by using protell99se. power supply module, signal - sampling module, mcu, keyboard input, lcd module, and cpld are designed. the third chapter completes the software design and the debugging in keil environment

    然後利用protell99se平臺完成pcb圖的設計和制板工作，根據晶元資料設計出供電模塊，信號採集模塊，單片機系統，日歷時鐘晶元，鍵盤輸入，液晶顯示系統，可編程式控制制模塊和各個模塊間介面。
  13. Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains. the data transaction protocol comes from the most basic work way of uart. when the master clock is 16. 7mhz, the pcm side and adpcm side clocks both are 2. 38mhz, the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14. 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14. 7 us

    在主時鐘為16 . 7mhz ， pcm數據端與adpcm數據端時鐘均為2 . 38mhz時，模擬結果表明從pcm的起始位輸入uart接收器到adpcm終止位輸出uart發送器的最大延遲為14 . 3 s ，從adpcm的起始位輸入uart的接收器到pcm終止位輸出uart發送器的最大延遲為14 . 7 s ，設計時盡可能的使編碼與解碼的時間相差不多，從結果看出基本達到這個要求。
  14. And the selection and design of switch - in module, switch - out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed

    論文中還給出了開關量輸入、開關量輸出、通信模塊、時鐘電路、數據存儲器、按鍵電路和頻率跟蹤電路等各功能模塊的選擇方法和設計原理。
  15. The whole pwm circuit contains two subcircuit, the front - end is pwm module that make up of the counter that based on nine mosfet true - single - phase - clock d flip - flop ; the back - end is demodulated module, which is consist of a three order chebyshev low - pass filter used trans - conductor capacitor. all the subcircuits are simulated. at last, an approving simulated result of the whole circuit is given too

    在調制部分，利用九管單相時鐘d觸發器構成計數器，並由此組成了脈沖寬度調制電路，同時給出了在典型溫度下的模擬結果;在解調部分，介紹了低通濾波器從無源到有源的設計方法，設計了三階切比雪夫低通跨導電容濾波器，同樣給出了相應的模擬結果;最後，作為將脈沖寬度調制電路和濾波器作為整體電路，以脈沖調頻波為輸入進行了模擬，取得了令人滿意的結果。
  16. Jdy - 280b double electromagnetic lock product characteristic : strong holding force, no left magnet easily installed, low noise, durable no mechanical failure with signal feed back function applications : can be used with intercoms and access control systems, especially for fireproof door working voltage : 12vdc 24vdc working current : 12vdc 0. 27a, 24vdc 0. 46a power consumption : 3. 3w, 3. 5w, absolutely insulative power supply mode : successively working temperature : - 40 50 dimension : 473 x 45 x 30mm weight : 3920g yiwu qimingxing computer company copy right

    Jdy - 280b雙開門磁力鎖產品特性:吸力強無剩磁安裝方便噪音低壽命長具故障保護功能，無機械故障可具資訊回饋功能鎖狀態有指示燈指示：鎖門時綠燈指示燈亮開門時，紅色指示燈亮帶鎖狀態指示燈及聯網信號輸出適用范圍：可與樓宇對講門禁系統配套使用特別適用於逃生門防火門電氣性能：電氣性能：使用電壓： 12vdc 24vdc電流： 12vdc 0 . 53a 24vdc 0 . 27a絕緣電阻測試： dc500v 1分鐘無擊穿通電形式連續使用溫度： 40 50外形尺寸： 473 x 45 x 30mm重量： 3920g
  17. Jdy - 280 electromagnetic lock with led product characteristic : easily installed, low noise and durable ; strong magnetic force, no magnet left when power off with led and network signal output built - in reverse wave protection function usage range : be used with intercoms and access control systems can be installed onto wooden door, metal door, glass door, fireproof door function : working voltage : 12vdc, 24vdc working current : 12vdc 0. 53a, 24vdc 0. 27a working condition : 40 50 working mode : cut off power to open wires are insulated, dc500v absolutely insulated in 1 minute. dimension of the magnet board : : 184 x 36 x 11mm dimension : 235 x 45 x 30mm weight : 1980g yiwu qimingxing computer company copy right

    Jdy - 280磁力鎖帶指示燈產品特性:安裝方便噪音低壽命長吸力強無剩磁內置反向突波保護功能適用於90開門，有門偵測信號帶鎖狀態指示燈及聯網信號輸出適用於樓宇對講門禁系統配套使用適用門型：木門金屬門玻璃門防火門電氣性能：工作電壓： 12vdc 24vdc工作電流： 12vdc 0 . 53a 24vdc 0 . 27a工作環境： 40 50工作方式：斷電開鎖鎖狀態有指示燈指示：鎖門時綠燈指示燈亮開門時，紅色指示燈亮絕緣電阻測試： dc500v 1分鐘無擊穿鐵板尺寸： 184 x 36 x 11mm外形尺寸： 235 x 45 x 30mm重量： 1980g
  18. According to different function, the hardware part is divided into processor module, analog signals input and converting module, digital signals module, communication module, clock module and display module

    按照功能的不同，硬體劃分成處理器系統模塊、模擬信號輸入和轉換模塊、開關量輸入輸出模塊、通信模塊、時鐘模塊、鍵盤顯示模塊、電源模塊。
  19. Dc 2060 has an output speed of 60 pages per minute ; this reduces sharply the time of printing documents

    Dc 2060每分鐘60頁的輸出速度，大大縮短了文件製作時間。
  20. This module works with a clock of 40mhz and its input accept lvds signal, output are both in lvds and ecl standard. the setting of the delay parameters is realized with vme software commands

    該插件的工作由40mhz時鐘控制，輸入電平為lvds 、輸出為lvds和ecl電平，其初始化通過vme總線加載，並具有多種編程下載方式。
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