時鐘頻率 的英文怎麼說

中文拼音 [shízhōngbīnlǜ]
時鐘頻率 英文
clock frequency
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 頻 : Ⅰ形容詞（次數多） frequent Ⅱ副詞（屢次） frequently; repeatedly Ⅲ名詞1 [物理學] （物體每秒鐘振動...
  • 率 : 率名詞（比值） rate; ratio; proportion
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 頻率 : frequency; rate
  1. The second parameter specifies the rate of the pixel clock in megahertz

    第2個參數指定的是像素時鐘頻率（單位為mhz ） 。
  2. A personal computer with a 100 - megahertz clock then executes 100 million stages per second

    一臺時鐘頻率為100兆赫的個人電腦每秒能執行一億次運算。
  3. One 1995 microprocessor uses this deeper pipeline to achieve a 300 - megahertz clock rate

    一臺1995年生產的微處理器用這種更先進的流水線操作可達到300兆赫的時鐘頻率。
  4. Electric - controller is nubbin in developping. we are based on designing to structure of circuit, we are dead against in time and stabilization for controlling and communications, precision and rapidity for transformation etc. we have completed to select on microprocessor, clock - frequency and a / d transfer. it carry out transformation for valve position signal, and select on solid - switch ac

    在控制器的電路結構設計的基礎上，考慮到通訊、控制的及時、穩定、轉換的精度和速度等幾方面，主要完成對微處理器的選擇、時鐘頻率和a d轉換器的選用，閥位變送功能的實現，固態交流開關和顯示器的選擇等。
  5. The high clock frequency requirements will have to be weighed against the need for tighter design criteria that ensure high noise immunity.

    高時鐘頻率的要求比高抗擾度的要求更為重要，因為高抗擾度可通過精心設計予以保證。
  6. After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages

    它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。
  7. Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. from the layout simulation result, under the 0. 18um process, the upper limit working frequency for the register file is 900mhz

    本文面向一款具有完全自主知識產權的64位高性能通用處理器，對其中具有代表性的128字65位12讀埠和8寫埠的通用寄存器文件進行研究，實現了它的高速讀寫全定製設計，版圖模擬結果表明，在0 . 18um工藝下，設計可以工作的時鐘頻率上限為900mhz 。
  8. As the semiconductor process technology steps into the deep sub - micro scale, the increasing number of transistors on single chip is making the digital system ever more complicated, and the clock frequency has already achieved the level of kilomega hz

    隨著半導體工藝水平步入深亞微米階段，單個晶元上的晶體管數越來越多，現代數字系統變得越來越復雜，時鐘頻率也己經能達到千兆赫茲以上。
  9. The clock frequency of the improving mcu should be higher than the highest frequency of pic16c5x mcu

    通過以上改進，使其時鐘頻率高於pic16c5x的最高時鐘頻率20mhz 。
  10. It is shown from fpga verification and computer simulation that the mcu core ' s maximum clock frequency and instruction efficiency are five times higher than those of mcs - 51 chips

    驗證結果表明，該mcu的最高時鐘頻率和指令執行效率等指標均優于mcs - 51的五倍以上。
  11. It is possible that the computer is of low grade, and the time frequency is too low, please change for a new computer

    有可能是主機檔次太低，時鐘頻率過低，請更換主機
  12. The clock frequency may be extended above 160khz without this error, however, by using a low value resistor in series with the integrating capacitor

    利用一個串聯在積分電容器電路里的低值電阻，時鐘頻率就可能被延伸到160khz以上，而沒有這個錯誤。
  13. With enlarging of circuits scale and speeding of clock frequency constantly, logic simulation is improving requirement constantly in tine consuming and accuracy

    隨著電路規模的不斷擴大和時鐘頻率的不斷加快，邏輯模擬對耗時和準確性的要求也不斷提高。
  14. In this paper, low power flip - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed

    與此相對應的，在本論文中，分別對將少時鐘負載或數據通路的負載的觸發器設計；減小時鐘信號幅度的觸發器設計；降低時鐘頻率的雙邊沿觸發器設計以及應用門控技術來減少觸發器無效跳變設計的觸發器結構進行了討論。
  15. The minimum clock frequency is established by leakage on the auto - zero and reference caps

    最小的時鐘頻率，由自動歸零和基準電容的泄漏值確定。
  16. The compaq server was a few years older, and had lower clock speed cpus

    Compaq服務器已經使用了幾年了， cpu的時鐘頻率較低。
  17. In the scheme, not only the rtlinux ' s double kernel structure and its virtual interrupt are adopted, which make the standard linux process as the lowest priority one in the real - time kernel, but also the 8254 is set to work in the one - shot model by using the kurt ' s utime package, which improves the clock frequency of the os and reduces the cpu ' s extra burden

    這種新的實時化方案利用了rtlinux的雙內核體系結構和中斷虛擬機技術，將標準linux進程作為實時內核的一個優先級最低的任務進行調度；同時還利用了kurt中utime軟體包將定時/計數器8254置為one - shot工作模式，從而既提高了操作系統的時鐘頻率，又解決了cpu額外負擔過重的問題。
  18. By careful selection of the ratio between this resistor and the integrating resistor ( a few tens of ohms in the recommended circuit ), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. 3

    通過小心選擇這個電阻和積分電阻之間的比值（在推薦線路里，大約是數十歐姆） ，比較器的延遲就可能被補償，最大的時鐘頻率可近似延伸到3 . 3倍。
  19. Dynamic power is dominant component of the average power dissipation in cmos circuits. and the value of dynamic power is determined by node capacitance, supply voltage, clock frequency and switching activity of cmos circuits. so most low power designs are achieved by reducing one or more those above parameters

    由於cmos電路的功耗與cmos電路的負載電容，電壓，時鐘頻率及開關活動性有關，因此在低功耗cmos觸發器設計過程中，許多低功耗設計技術都可以歸結到通過減小上面的參數來達到低功耗的目的。
  20. Now, the programmable chip ' s clock becomes faster and faster, the capability of programmable chip is improved very fast also, so more complex function can be implemented in one chip. this design can implement as jpeg coding chip in fpga, it can be used as ip core to other designs

    隨著可編程晶元時鐘頻率的不斷提高，晶元容量的不斷增大，可以在晶元上實現更復雜功能，這又使可編程晶元的應用更加廣泛。本設計可以單獨作為編碼器在fpga上實現，也可以作為一個ip核嵌入到其他設計中去。
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