時間電路 的英文怎麼說

中文拼音 [shíjiāndiànlù]
時間電路 英文
time circuit
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 間 : 間Ⅰ名詞1 （中間） between; among 2 （一定的空間或時間里） with a definite time or space 3 （一間...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 時間 : time; hour; 北京時間十九點整19 hours beijing time; 上課時間school hours; 時間與空間 time and spac...
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. The new system consists of a single - chip computer system ( at89c51 + psd311 ) and alow power consumed analyzer by applying a new adc chip ads774, and a dead - time correcting circuit is designed to correct the collecting time

    本系統由單片微機系統（ at89c51 + psd311 ）組成多道緩存，由低功耗模數轉換器組成分析器，與微型計算機通過列印并行介面實現數據通訊，並含有死時間校正電路。
  2. Maintaining a caesium beam clock as the hong kong time standard and providing time signals for radio broadcasts, automatic telephone answering service and synchronisation of clocks via internet

    操控銫原子鐘作為香港的時間標準，以及透過各電臺自動答覆電話查詢服務及網際網路校對時鐘服務提供報時訊號
  3. Maintaining a caesium beam clock as the hong kong time standard and providing time signals for radio broadcasts, automatic telephone answering service and synchronization of clocks via internet

    操控銫原子鐘作為香港的時間標準，以及透過各電臺、自動答覆電話查詢服務及網際網路校對時鐘服務提供報時訊號；
  4. Network call signaling protocol for the delivery of time critical services over cable television networks using cable modems

    使用電纜數據機通過電纜電視網傳送時間嚴格的服務用網路呼叫信令協議
  5. Contrapose to the instability of the third - order charge - pump pll system, the loop optimization method is employed in system level design to decide the bandwidth and phase margin, therefore the loop bandwidth locates at the maximum phase margin to guarantee the stability of the system. according to tsmc 0. 35 m sige bicmos model, the sub - circuits in the designed pll and the whole system are simulated and verified by the cadence spectre

    5 .根據tsmc0 . 35 msigebicmos工藝模型，利用cadencespectre模擬軟體對所設計的電荷泵鎖相環路中各個模塊及整個系統進行了模擬模擬，模擬結果顯示，在1 . 5v電源電壓下，頻率為200mhz的參考輸入信號，輸出中心頻率為800mhz ，分頻電路採用4分頻，環路帶寬為10mhz ，捕獲時間大約為0 . 92 s ，功耗大約為15mw ，達到了設計指標。
  6. A theoretical formula was applied to this process so that the open circuit voltage could predict the limit of deoxidization reaction

    通過電池電動勢與時間關系的數學模型，得出外電路電壓與熔池中氧含量的關系，從而根據外電路電壓可以預測脫氧反應進行的程度。
  7. In order to understand the mechanism of short - circuited deoxidization, an experiment was designed and performed for measuring the relation between the open circuit voltage of a deoxidization device and the process time

    摘要為了解固體電解質脫氧的內部機理，對氧化鋯固體電解質電池短路脫氧過程中的外電路電壓隨時間的變化進行了研究。
  8. Sep is a kind of bioelectric reaction which is characterized by time - locked and special response. the response can be reorded at the any part of special somatosensory system including from derma - tomes to peripheral nerve, spinal posterior root, et al, when stimulated in a proper style

    體感誘發電位是對軀體感覺系統的任意一點包括從皮膚節段到外周神經干、脊髓神經后根等，給予適當形式刺激后，在該系統特定通路上的任何部位均可檢出與刺激有相對固定的時間間隔和特定形式的生物電反應。
  9. This paper presents a method that chopping wave is done by switch devices which consist of three - level resistance regulating module and intelligence power module ipm, and which realizes constant - current discharge of storage battery. to achieve the intelligence control of the drive protection and the discharge process of ipm, the paper designs circuit formed by igbt threshold drive pulse pwm signals. ipm fault - blocking protection circuit and microcomputer 80c196. the devices can accurately control the 0 ~ 150a discharge current and the discharge time of the storage battery and calculate the releasing power

    實現蓄電池恆流放電過程智能控制是蓄電池放電裝置發展的必然趨，本文提出了一種通過三極電阻調節模塊和由智能功率模塊ipm為開關器件進行斬波從而實現蓄電池恆流放電的方法。為達到對ipm的驅動保護和放電過程的智能控制，文中設計了igbt門極驅動脈沖pwm信號形成電路和ipm故障封鎖保護電路及由單片機80c196為核心的微機控制器。本裝置能夠對蓄電池進行0 150a放電電流及放電時間的精確控制及釋放容量的計算。
  10. In order to obtain the most economic benefits, the paper utilized the theory of " homalographic characteristic " and " share alike compensation current characteristic " to build up the best compensation relation for " hour - current " curve applied to transformer substation and for " length - current " curve applied to distribution line

    以獲得最大經濟效益為目標，利用「等面積特性」和「補償電流等分特性」理論。推導了應用於變電站的「時間?電流」曲線關系中存在的最佳補償關系，以及應用於配電線路的「長度?電流」曲線關系中存在的最佳補償關系，及補償后的經濟效益計算模型。
  11. Become a kind of new electronics circuit - current - mode circuit. it is replacing the traditional design method of the voltage - mode in the high frequency high - speed signal processing realm 。 this thesis mainly discussed the modified second - generation current conveyors based on the current - mode kinds of new cuicuit components, they are stronger modified standard current - mode parts in fuctions on this foundation. mainly including the modified differential difference current conveyor ( mddccii ) 、 the fully balanced second generation current conveyor ( fbccii ) 、 ( full balances ) four - terminal floating nullor ( fbftfn ) and the current differencing buffered amplifier ( cdba ), they are all function very strong standard current - mode parts, they all can provide some circuit functions of better than general operation amplifier, because they have the voltage importation and the current importation, therefore use it since can carry out the voltage - mode signal processing circuit expediently, can also carry out the current - mode signal processing circuit expediently, and have to increase the benefit bandwidth to accumulate more widely than the voltage - mode, but have their advantages more according to the current - mode filter of the modified current conveyor, because it constitutes in brief, the filter wave function is stronger and they are better than in general use operation amplifier of many advantages, be easy to composing for example 、 high speed 、 frequency bandwidth 、 the power supply voltage requests low 、 consume small, the impedance is different from etc. advantages, otherwise they have biggish dynamic range, and flexible circuit synthesize, so they are the best active parts

    從第二代電流傳輸器ccii入手，重點研究了以下幾種改進型的第二代電流傳輸器:改進的差動差分電流傳輸器mddccii 、全平衡第二代電流傳輸器fbccii 、多輸出四端浮地零器ftfn 、全平衡四端浮地零器fbftfn 、電流差分緩沖放大器cdba的電路結構及其模型。然後在此基礎上系統地研究了基於這幾種改進型的第二代電流傳輸器的濾波器的設計方法，主要方法和結果如下:利用mddccii設計了差分式連續時間電流模式低通、帶通濾波器;電流模式跳耦結構考爾低通濾波器;利用fbccii設計了帶通二階節濾波器及電流模式雙二階通用濾波器;設計了基於多輸出端ftfn的電流模式二階通用濾波器電路;通過數字化開關選擇的基於fbftfn的電流模式通用濾波器;設計了基於最少個數電流緩沖放大器（兩個cdba ）的多功能通用電流模式濾波器及其在非理想因素情況下分析。設計濾波器的主要方法是採用級聯設計、運算模擬（信號流圖法）和反饋設計（跳耦法） 。
  12. Since high performance control logics are usually hard for non - scan test generation, dft structures could be embedded as offsets in tradition, while it will cause manufacturing cost increase and performance overhead. in this paper, an indirect test generation method based on retiming is proposed, which could dramatically reduce the cost of non - scan atpg without any loss of original optimized attributes. experiments on some iscas 89 benchmarks show the benefits of our approach in enhancing atpg of performance - driven logic

    對性能驅動控制邏輯進行測試生成難度較大，通常要加入可測性結構，但會影響原電路優化性能並增加生產成本.本文以重定時理論為基礎，提出了對高性能時序電路進行間接測試生成的方法，這種方法在不影響原電路任何優化特性的前提下，可顯著降低測試生成時間，提高測試生成質量.在iscas 』 89部分基準電路進行實驗，結果證明了其有效性
  13. In order to eliminate the sequence conflict of synchronous sequential circuit and shorten the designable time of integrated circuits, the algorithms of retiming is deeply researched in this paper

    本文對重定時演算法進行了深入研究，目的在於消除同步時序電路的時序沖突，從而縮短集成電路的設計時間。
  14. As emphasis, we propose a new backward width - flrst search circuit partitioning method with flip - flop as core for synchronous sequential circuits. and then based on it, we develop a new circuit parallel tg algorithm

    最後重點對電路并行方法進行了研究，提出了一種新的以觸發器為核且消除大功能塊之間反饋的寬度優先反向搜索同步時序電路劃分方法。
  15. Some theoretical extensions are first made in this paper, with the following concepts, theorems and models presented - partial derivative and high - order partial derivative of waveform polynomial for describing the relation between input transitions and output transitions and redefining circuit sensitization ; the concept of waveform polynomial vector for describing a circuit with multiple inputs and outputs, especially for the unified description of circuit modules ; a sensitization theorem for sequential circuits for the purpose of exact timing ; theorems for transition numbers in circuits used to solve problems on noise, power consumption and etc ; waveform polynomial description for sequential circuits used to give a unified form for the function and timing behavior of a sequtial circuit ; and a data structure of generalized list for the representation and manipulation of waveform polynomial

    波形多項式偏導和高階偏導的新概念，用來精確描述輸出跳變與輸入跳變之間的關系，並在本文中用來重新定義了電路的敏化和冒險；波形多項式向量的概念，用於形式化描述實際中的多輸入多輸出的電路，特別是用於統一描述電路模塊的功能及定時行為；時序電路的敏化定理，用於時序電路精確定時分析；波形多項式描述跳變及跳變數的定理，用於噪聲、功耗等問題的描述；時序電路的完整波形多項式描述，用於時序電路功能和定時行為的統一描述；波形多項式的多項式符號表示和運算的模型以及數據結構，用來實現對波形多項式比較有效的描述和運算。
  16. Abstract : the principle and application of several kinds of opening switches with microsecond conduction time for inductive energy storage of high power pulse technology are introduced, and the characteristics of the switches are reviewed briefly

    文摘:介紹了幾種用於脈沖功率電感儲能技術的微秒級傳導時間斷路開關的原理和應用，並就它們的各自的特點進行了評述。
  17. High - voltage cubicles, current transformers, cable heads, hour meters, switches, transformers, circuit beakers, etc

    高壓制櫃、電流變壓器、電纜前端、時間電表、電閘、變壓器及斷路器等
  18. The condition that exists when two coupled circuits are adijusted so that the outp - ut impedance of one circuit equals the input impedance of the other circit connec - ted to the first, there is a minimum power loss between two circuits

    指一個存在的條件，當調整兩個偶合電路使得其中一電路的輸出阻抗與另一電路的輸入阻抗相等進稱之，當他們連接的阻抗相等時，兩電路間的能量損失最低。
  19. We first propose and implement a sequential word - level pattern parallel fs algorithrn for synchionous sequential circuits. differing from other similar algorithins, it utilizes the relative independence of every fault test sequence generated by the g - f two - value tg algorithm, pwtitions and dynamically mounts test pattem, avoids redundant simulation for added synchlronous sequence, and gets better results

    首先提出並實現了一個新的同步時序電路單機字級測試碼并行fs演算法，該演算法與現有同類方法的不同在於，利用確定性g - f二值tg演算法的每個故障測試序列之間的相對獨立性，對測試碼進行分解並動態組裝，避免了對添加的同步序列的冗餘模擬，效果較好。
  20. It includes the design of trigger circuit, high speed clock circuit, a / d digital and data acquisition circuit, time inter - plug circuit and pci interface circuit 。 3. the function debug of hardware and the result analysis

    主要包括觸發電路的設計、高速時鐘電路設計、 a / d數字化與數據採集電路設計、時間內插電路設計和pci總線介面設計。 3 .硬體功能調試及其結果分析。
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