晶元級 的英文怎麼說

中文拼音 [jīngyuánjí]
晶元級 英文
onc on chip
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 級 : Ⅰ名詞1 （等級） level; rank; grade 2 （年級） any of the yearly divisions of a school course; gra...
  1. We ' re talking 500 acres of hardware, cray super computers, ampliation chips

    那裡是佔地五百畝的硬體，超級cray計算機目前最快，最貴的，擴充的晶元
  2. This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga

    本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。
  3. This paper refers to several creation in compatibility with large volume of fed display and conversion of different video signal. it firstly used special central chip al300, designed correlative circuits, successfully developed vga full - color fed console system, compatible with resolution 1280 1024, achieved functions such as multi - video signal conversion and interleaving, met vga ’ s resolution of fed. it firstly designed and fabricated vga interface and separated video interface - - s - video, converting several video signals to 24 bits full - colored digital image signal in fed driving system, achieved separation of luminance signal and chromatism signal, enhanced the bandwidth of luminance signal

    首次採用平板顯示專用控制晶元al300 ，設計並製作了相關配套電路，支持的最高解析度是1280 1024 ，實現解隔行和多種視頻格式轉換的功能，滿足了fed顯示屏對vga解析度的要求。首次在基於fpga的vga級彩色fed控制系統中設計並製作了vga介面和分離電視信號s - video介面，可以將多種視頻信號變換為fed驅動系統可用的24位彩色數字圖像信號，實現亮度信號和色差信號的分離，提高了亮度信號的帶寬。
  4. An invariable current single power supply administering chip

    一種恆流單級電源管理晶元
  5. The 1mhz fixed frequency switching allows for tiny external components and the regulation scheme is optimized to ensure low emi and low input ripple. an external resistor sets the full - scale led current, while two digital inputs control on / off and select amongst three levels of brightness. the circuit operates in 1x mode until just above dropout

    工作在1mhz固定頻率，採用線性調制模式使輸入紋波大大減小;利用一個外部電阻可以設置滿量程led電流;外接兩個數字信號控制晶元開關並選擇led三級亮度中的一級;具有過溫、過壓/欠壓等保護功能，工作溫度范圍為- 40 + 85 。
  6. Measurement challenges for on - wafer rf - soc test

    晶圓上測試射頻系統級晶元的挑戰
  7. Ssb : super south bridge

    超級南橋晶元
  8. In this project, the kernel chip is xc2vp4, which is a platform fpga manufac - tured by xilinx co. ise7. 1i foundation which is the latest and integrated eda devel - oping tool is used in the software developing. modelsim se6. 0 and ise simulator are the simulation tools. synplify pro8. 1 and xst are the synthesis tools

    本課題硬體採用xilinx公司xc2vp4平臺級fpga為核心控制晶元，軟體採用xilinx公司最新集成化eda開發工具ise7 . 1ifoundation ，模擬工具modelsimse6 . 0 ，綜合工具synplifypro8 . 1等設計完成，高速電路採用lvds信號進行連接。
  9. Confronted with the explosion of communication traffic in internet, the communication networks architects make great efforts to provide scalability for switch architecture in the current routers and switches. single - stage switches are hard to implement in scalable switches for the limitation of pins and complexities of ic design

    交換網路處理的業務流量增長要求交換網路的容量需要不時地進行升級，單級交換機由於受晶元的管腳和ic實現復雜度的限制，無法應用於大規模可擴展交換機，因此，採用由多個交換單元構成的多級網路是目前常用的解決方案。
  10. The laser unit, because of its monochromaticity and small divergency, is used as sensor ’ s light source. devices and chips provided with high - speed responsing and processing capabilities are employed. as a result, the achieved uncertainty of time measuring is 125 ps, demonstrating an accuracy improvement in magnitude of an order

    在設計製作中採用了單色性和方向性好的激光作為光源，選取了高速響應和有高速處理能力的一系列器件、晶元，因此時間測量的精度達到了125ps ，比以往的測試方法提高了1個數量級以上，速度測量精度達到掃描速度的0 . 1 % 。
  11. On the internet site placed by the enterprise ihge fuchs elektronik gmbh, you receive views on smart card machines, coin automat as well as on gaming machines

    Ihge fuchs elektronik gmbh是一家高級企業，該企業針對客戶需求製造專門的晶元卡自動生產機，硬幣自動設備，自動游戲機。
  12. Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co. and the detailed analyses of typical examples are also given

    結合altera公司classicep610晶元的結構，研究了將演化演算法應用於函數級數字組合邏輯電路的硬體演化，並且對典型實例進行了詳細分析。
  13. Through analysising the characteristics of the power system with floating neutral point deeply, the paper puts forward a new plan of single - phase to ground fault line selection on the base of s ' s signal injecton method and gives the hardware and software design. in this design, the high speed sampling and data processing is carried out through using dsp processor ; the large electrice current is drived through the application of a high - performance audio power amplifier and transformer ; the communication between host computer and detectors is realized through rs485 bus technology ; the difference multilevel frequency - selected amplifier is designed and the feeble signal of space is sampled on the base of the theory of magnetic induction ; the interface between dsp and exterior chip and rs485 interface logical is designed through using fpga ; the using of lcd module and keyboard interfacing chip makes the interface between human and machine ; the programme of host computer and detectors is designed through using blocking design method

    在本設計中，採用高速的dsp處理器，實現了對故障特徵信息的高速採集與處理;採用大功率的功放晶元與變壓器配合的方法，實現了大電流信號的驅動輸出;採用485總線技術，組建了裝置主機與多探測器之間的主從式通訊網路，實現了多干擾條件下裝置主機與多探測器的可靠通訊;設計了差分式多級選頻放大電路，採用磁感應的方法實現了對空間微弱信號的接收;利用fpga技術，實現了控制器與多外設的介面及數字信號的串並轉換;採用了先進的lcd液晶顯示模塊及鍵盤介面晶元，設計了人機信息交互的介面;採用了模塊化的軟體設計方法，開發了裝置主機及探測器的軟體程序。
  14. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  15. In active section, in order to meet performance of out put power above 10dbm, the power amplifier module of ka - band is fabricated by using hmc283 to achieve the 14db conversion gain. there are five parts that include of waveguide - to - microstrip ? mixer ? filter ? power amplifier and waveguide - to - microstrip. input signal ' s power is 10dbm, after it pass waveguide - to - microstrip, it ' s frequency is escalate from 30ghz to 35ghz

    該組件由五個部分組成：功率為10dbm信號經過波導? ?微帶過渡，然後混頻，濾波將30ghz提高到35ghz濾除不需要的諧波鏡頻以及三階交調信號，為了彌補混頻濾波的變頻損耗，加一級功率放大器，此放大器採用hittle公司hmc283晶元，此上變頻放大組件完成了上變頻?濾波?放大功能。
  16. Description of some of the expected future developments in time and frequency standards and distribution, including such topics as chip - scale atomic clocks ( size of a rice grain, powered by aa battery, potentially capable of low cost mass production )

    介紹一些未來可預期的時間頻率標準和發布技術的進展，包括諸如「晶元級的原子鐘」 （大米粒尺寸，由aa電池供電，具有低成本大批量生產潛力） 。
  17. As examples of vfg, this paper introduces in detail the system - and chip - level vfg of electronic devices

    作為虛擬特徵生成實例，本文以電子設備概念設計為例，詳細介紹了系統級和晶元級的虛擬特徵生成方法。
  18. For the training of professional system, the identification of suppliers, and the practical project, sv has the professional project engineers advanced in the av technique in china, who can offer blue print of design, installation, training and the maintenance of chip level

    專業系統的培訓與廠商認證及豐富的實際工程經驗，索訊擁有國內最早從事av技術的工程技術人員，能夠為客戶提供方案設計、安裝、培訓與晶元級維修
  19. The " chip _ level " fault detection was implemented by means of diagnosing technology and experimental methods. the experimental results indicate that this system is fast, accurate, ease to use, portable and applicable for practicable use

    通過軟體、硬體技術的結合，採用多種檢測技術及實驗方法，達到了晶元級故障定位的設計目的。實驗結果表明，本系統具有故障定位準確、檢測速度快、操作簡便和便攜式等特點，具有較高的實用價值。
  20. Similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard - cell methodology can be divided into two levels : inner standard - cell and among standard - cells. however, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard - cell. because the router cannot impose the characteristic of the transistors in the standard - cell, it may reduce the performance of the whole chip

    通常，基於標準單元布圖模式將版圖綜合劃分成單元內與單元間兩個層次，以簡化晶元級自動版圖綜合問題的復雜性；但隨著晶元規模的不斷擴大，基於主要以手工定製的小規模標準單元，晶元級版圖綜合問題的復雜性不斷增大，且標準單元間布線無法充分利用單元內晶體管特徵，影響晶元的整體性能。
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