最後的主線串 的英文怎麼說
中文拼音 [zuìhòudezhǔxiànchuàn]
最後的主線串
英文
last primary string-
Firstly, reliability models of different element are built in the paper. secondly, the reliability parameters of virtual series element on the main feeders are computed by series equivalent method. lastly, indices of different load points are calculated by the method of minimal cut - set
文中首先建立了不同元件的可靠性模型，其次通過串聯等值法求取各主饋線上的虛擬串聯等值元件的可靠性參數，最後應用最小割集方法計算各負荷點指標，從而得到系統各項可靠性指標。Again, it is best to consult the installation instructions supplied with the device for detailed instructions, but the basic process is to connect the ipaq to a host computer and transfer the jffs2 file using the ymodem protocol to the ipaq over the serial line
另外，最好查閱隨設備提供的安裝說明，以獲得詳細說明，不過，基本的方法是，將ipaq連接到一個主機計算機，然後通過串列線將jffs2文件傳輸到ipaq上（使用ymodem協議） 。Finally, the universal serial bus ( usb ) was adopted as the system ' s communication bus. usb has a preferable data transmission rate, support pc ' s plug - and - play architecture and bus - powered ( max. 500ma )
最後經過比較，論文採用了具有較高傳輸速度、支持即插即用和熱插拔，還有主機供電（最大500ma ）等優良性能的通用串列總線（ usb ） 。The thesis is composed of 9 parts : the background, significance, main topics and innovations in the thesis are introduced in chapter 1 ; in chapter 2, the main function and performance of interface circuits are described from the view of system by using the example of gigabit ethernet ' s transceiver ; the transmission media ' s frequency characteristics and model are analyzed for the high - speed data transmission system in chapter 3 ; the line driver is presented in chapter 4 ; the equalization principles for high - speed data transmission system are introduced in chapter 5 ; a novel adaptive equalizer for 1000base - cx transceiver is presented in chapter 6 ; in chapter 7, a fixed equalizer for 2. 5gbps transceiver is described ; in chapter 8, layout design and measured results are discussed ; at last, the conclusions are drawn in chapter 9. during period of finishing the thesis, i read lots of literatures about the interface circuits in high - speed data transmission system, studied their principles and design techniques, and designed : 1 、 the line driver for 2. 5gbps baseband copper cable transceiver ; 2 、 the fixed equalizer for 2. 5gbps baseband copper cable transceiver ; 3 、 the fixed equalizer for 1. 5gbps sata ( serial at attachment ) transceiver ; 4 、 an adaptive equalizer for 1000base - cx transceiver
論文由9部分組成：在第一章引言中介紹了論文的背景、意義、國內外研究現狀，以及論文的主要內容和創新；第二章以千兆位以太網為例，從系統的角度介紹了高速數據傳輸系統介面電路的主要功能和性能指標；第三章分析了高速數據傳輸系統的傳輸介質的頻率特性和模型；第四章描述了線驅動器的設計原理及其電路實現；第五章描述了高速數據傳輸系統的均衡原理；第六章描述了適用於1 . 25gbps基帶銅纜收發器系統的自適應均衡器的設計原理和電路實現；第七章描述了適用於2 . 5gbps基帶銅纜收發器系統和1 . 5gbps串列硬盤介面（ sata ）收發器系統的固定均衡器的設計原理及其電路實現；在第八章中分析了電路的版圖設計及晶元測試結果；最後，第九章總結了全文。在完成論文期間，查閱了大量的有關高速數據傳輸系統介面電路方面的文獻，較系統地學習了線驅動器、傳輸線和均衡器等方面的理論知識和電路設計原理，設計了用於： （ 1 ） 2 . 5gbps基帶銅纜收發器系統的線驅動器； （ 2 ） 2 . 5gbps基帶銅纜收發器系統的固定均衡器； （ 3 ） 1 . 5gbpssata系統的固定均衡器； （ 4 ） 1 . 25gbps基帶銅纜收發器系統的自適應均衡器。分享友人