標準模擬電路 的英文怎麼說

中文拼音 [biāozhǔndiàn]
標準模擬電路 英文
standard analog circuit
  • : Ⅰ名詞1 [書面語] (樹梢) treetop; the tip of a tree2 (枝節或表面) symptom; outside appearance; ...
  • : Ⅰ名詞1 (標準) standard; guideline; criterion; norm 2 (目標) aim; target Ⅱ動詞1 (依據; 依照)...
  • : 模名詞1. (模子) mould; pattern; matrix 2. (姓氏) a surname
  • : 動詞1. (設計; 起草) draw up; draft 2. (打算; 想要) intend; plan 3. (模仿) imitate
  • : Ⅰ名詞1 (有電荷存在和電荷變化的現象) electricity 2 (電報) telegram; cable Ⅱ動詞1 (觸電) give...
  • : 1 (道路) road; way; path 2 (路程) journey; distance 3 (途徑; 門路) way; means 4 (條理) se...
  • 標準 : (衡量事物的準則; 榜樣; 規范) standard; criterion; benchmark; pip; rule; ètalon (衡器); merits
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  • 電路 : [訊] circuit (ckt); electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail

    文章根據相關提出並實現了一種專用晶元的設計方案,並對其中主要功能塊和關鍵演算法作出了詳細說明,包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。
  2. For electronic circuits, we usually use standard circuit - simulator software to predict the behavior of each circuit in the population

    來說,我們一般會用軟體,來預測族群中每個的行為。
  3. Have the profession background of mechanics , electronics and communication university degree , be familiar with simulative electrocircuit , digital electrocircuit as well as microcomputer principle , be able to master the technique characteristics of fire electronics product and concerned national standard through self - study

    有機械,子與通訊大學專業背景,對、數字、微機原理有較熟練掌握,經過自己學習能掌握消防子產品技術特點和有關國家
  4. Gb1094. 5 - 85 power transformers part 5 ability to withstand short circuit only applies to power transformers, not to balanced transformers. if short - circuit test on balanced transformers can be performed by means of single phase supply instead of three phase supply, and other special transformers can also be done in this way, so it is very significant to improve test capacity of transformer laboratory in our country

    變壓器的短強度只能通過短試驗來驗證,國家gb1094 . 5 - 1985 《力變壓器第5部分承受短的能力》只適用於力變壓器,對平衡變壓器等特殊變壓器並無具體規定,對于平衡變壓器,如果可以用單相源預先短三相源的短試驗,那麼其它特種變壓器的短試驗也可以參照進行,這對提高我國變壓器試驗室的試驗能力具有重要意義。
  5. This paper considers two controllers with different feedback signals ? the ac current phase angle of converter transformer and the ac voltage magnitude of inverter bus, respectively. pscad / emtdc simulation software is used for the controller testing. the test models used for the analysis are the cigre hvdc benchmark systems with different scr at the inverter side

    為了驗證該控制方式的有效性,本文採用了磁暫態軟體pscad emtdc ,在國際大網會議cigre提出的hvdc型上,用逆變側短比不同的系統對調制控制器的性能進行了測試,調試出了調制控制器的各參數值。
  6. The chip can be widely used in mp3 player, pda, digital camera, cells phone and portable products etc. this thesis first introduces the basic theory of switching power supply. the operating theory of this circuit has been demonstrated. the operating principle and simulation analysis about band gap reference, self - biased current source, one shot circuit, hysteresis comparator, and current - limit circuit have been particularly expounded in this thesis

    本文首先闡述了開關源的工作原理,詳細介紹了本的整體工作原理,最後重點介紹了自偏置流源、基、單穩態觸發器、峰值流限制及低壓遲滯比較器的工作原理,並利用eda工具larker ? ams 、 hspice對進行了完整的設計和,給出了合理的數據,各子特性參數均達到或優于設計所需指
  7. In the meantime, the all sub - circuits are also designed and emulated carefully including inverter, rs type flip - flop, voltage reference circuit, error amplifier, voltage comparator, sawtooth - wave generator, pwm comparator, soft activation circuit and so on. as a result, all of the sub - circuits answer the requirements. this chip has taped out with the 0. 5um mix - signal process of csmc

    本文利用cadenceeda集成設計工具、 spectres工具,對集成內的各個塊包括反相器、基本rs觸發器、基、誤差放大壓比較、鋸齒波振蕩發生、 pwm比較、軟啟動、驅動等進行了具體的設計和,且達到了預先設定的指
  8. Based on iec standards, the methods of designing square demodulator, bandpass - weighted filter, and smoothing filter are presented. besides, the signal conditioning circuits and online statistical analysis methods of instantaneous flicker value are given. matlab simulink is also used to simulate the measuring process of voltage fluctuation and flcker

    基於iec要求,設計了實現數字式壓閃變測量的平方解調器、帶通加權濾波器、平滑濾波器等各環節,給出了信號調理和瞬時閃變值在線統計分析方法,並應用matlab系統工具simulink對壓波動和閃變測量全過程進行了數字化
  9. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並塊串列化器和解串列器採用單元的方法設計,論文討論了對幾種時鐘同步式以及串並轉換結構的權衡和實現,並對所設計的結構進行了verilog驗證。
  10. And then, based on the above theories, the circuit design and simulation means have been concretely applied in the internal modules of voltage reference, bias circuit, oscillator, error amplifier and drive circuit of the chip and so on. the relevant design indexes are successfully achieved. at last, the whole circuit simulation and layout design are completed

    在此理論基礎上對該源晶元內部的各個塊,如壓基源、偏置、振蕩器、誤差放大和驅動塊進行了具體的設計和分析,且達到了相應地設計指,最後,完成了整體和版圖設計。
  11. Subcircuit models are designed and simulated, which includes bias current source, voltage reference, error amplifier, pwm comparator, driver circuit, protection circuits for over - temperature, over - current. at last, combined with periphery component, the circuit is simulated, and the result meets the anticipant requirement

    並對集成內的各個塊包括流偏置、基、誤差放大、三角波振蕩發生、 pwm比較、驅動、過熱保護和過流保護等進行了具體的設計和,並對整體應用進行了,結果均達到了預先設定的指
  12. An improved high - resolution current - mode sorter is presented. its structure complexity is o ( n ), which is crucial to the expansion of its size, and its dynamic range is large. only one clock signal and one reset signal are needed. no biasing signal is required. the operation point is constructed according to the input current, so it is self - adaptive, which is very important for an all - purpose component. in average value circuit, subtraction circuit, winner - take - all ( wta ) circuit and control circuit, it has good performance even at a large input current. this sorter has high precision, high resolution and low power, as has been proved via hspice simulation. it can be implemented in the standard digital cmos technology and widely used in many fields, so it is of great value in applications

    提出了一種改進的高精度流型排序.它的結構復雜性僅為o ( n ) ,便於擴展;動態范圍大;它是自適應的,工作點由輸入流確定,故不需要偏置信號,這對作為通用器件使用的排序來說是很重要的.通過利用平均值、減法、 wta和控制,可以使該在大輸入流下依然保持高性能. hspice表明該具有高確性、高精度、低功耗的特點.它能用數字cmos工藝來實現,可以被應用於很多領域,具有很高的應用價值
  13. Also discussed the methods on how to realize the cwt both in time - domain and frequency - domain and how to design the gm - c bandpass filter used in realization of cwt. in order to optimize the performance of gm - c filter, linearization techniques are investigated and proposed. due to process variation and parasitics, an automatic tuning is designed for center frequency / 0 and quality factor q also, in this thesis, 16 - channel analogue cmos cwt circuit has been realized

    論文圍繞連續小波變換的實現這一熱點問題,討論了連續小波變換的時域和頻域實現方法;具體分析了并行結構與串列結構的優缺點;研究了頻域法中的跨導-容帶通濾波器的設計;給出了改善跨導輸入級傳輸特性的線性程度並擴大線性范圍的具體方法;設計了片內自校正(可調諧)環節使濾波器參數自動調整到設計值;最後給出了16通道濾波器組實現小波變換的方法。
  14. With the development toward sub - micron and deep sub - micron technologies, cmos will have extremely wide market prospects, because its low cost and easy of implementation. hence all the simulation of this paper uses the csmc 0. 6 m standard cmos process

    cmos工藝作為數混合集成的主流工藝,隨著cmos技術的發展,具有廣泛的市場前景,本文就是在在csmc0 . 6 mcmos工藝庫下進行的。
  15. At last, the layout is verified with cadence verification tools, dracula. drc ( design rule cherker ) and lvs ( layout versus schematic ) have been done successfully, which improve the feasibility of the layout design. so the whole ic design flow, from the front end to the back end of a circuit design, is completed

    接著應用無錫上華0 . 6umcmos工藝提供的元器件型參數進行了,並根據尺寸設計規則設計了整體的的版圖,最後運用cadence中的版圖驗證工具集dracula對版圖成功地進行了drc ( designrulecherker ) 、 lvs ( layoutversusschematic )驗證,證明了版圖設計的可行性,完成了ic設計從前端到後端的設計流程。
  16. At the same time, the performance and the security problems appear and cannot be ignored. so it ' s urgent to build a management system that can manage the analogous devices and digital devices together and can correspond with the catv trunk network management system. to meet the need analyzed above, we recommend using snmp to build the broadband hfc access network management system

    為了保障網高效安全地運營,寬帶hfc接入網需要一套網管系統;為了與現代有線視網的干線網管系統相協調,寬帶hfc接入網需要一套的網管系統;為了能同時支持業務和數字業務的管理,寬帶hfc接入網需要一套能同時管理設備和數字設備的的網管系統。
  17. The main contents are as follows : the structure of mixed - signal circuit which newly - defined in ieee1149. 4 std is analyzed in detail, especially anolog boundary module and test bus interface circuit. on the basis of mixed - signal boundary scan technology, a scheme of mixed - signal boundary - scan test system is presented and the hardwares are implemented, including the controller and display unit

    主要研究的內容以及所作的工作如下:詳細分析了ieee1149 . 4中針對混合信號測試新增的結構,即邊界塊及測試介面。基於混合信號邊界掃描技術,提出混合信號邊界掃描控制器的設計方案並實現了其硬體設計,包括邊界掃描控制塊、顯示驅動塊等。
  18. The system ensures transformer to " credibility, safety and economy running. by analyzing transformer criterion and picking up the work criterion and test requirement and process of power transformer test ; according to the requirement of " synthesis function, computer structure, screen watch, intelligence management ", the performance and parameter integrated measure system of oilfield power transformer is designed ; according to the demands of transformer test criterion and computer control technique, the computer test methods are worked out ; aiming at the special instance of power company, the online measure of short - test in

    通過分析變壓器,整理出滿足力變壓器試驗的工作、試驗要求和步驟;按照「功能綜合化,結構微機化,監視屏幕化,管理智能化」的要求,設計了力變壓器性能參數綜合檢測系統;根據變壓器試驗和計算機控制技術,設計出符合微機檢測的方法;對變壓器試驗中的短試驗的在線測量作試驗室研究,說明變壓器試驗在線測量是可行的。
  19. However, to the design of analog circuit, it is a challenge when its supply voltage is low o now the typical supply voltage of analog circuit is about 2. 5 - 3 v, but the trend suggests it will be 1. 5 v, even much lower. under this condition, great effort of research members domestic and abroad is devoted to the design of low - voltage circuit structure with standard cmos processes in the analog ic, one of the typical circuits is operational amplifier, and many analog circuits can use it.

    然而,壓的下降對的設計是一個挑戰。如今的典型壓大約是2 . 5 3伏,但是發展的趨勢表明壓將是1 . 5伏,甚至更低。在這種情況下,國內外研究人員的很多精力花在設計適用於cmos工藝的低壓結構。
  20. As a result, it is necessary to add a digital interface to trng which is realized by analog circuit

    因此就需要為以為核心的真隨機數發生器添加數字介面,以符合規定的總線協議
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