模計數器 的英文怎麼說

中文拼音 [mójìshǔqì]
模計數器 英文
module counter
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 計數 : count; tally; counting計數卡 numbered card
  1. On one hand, the focal point that the interface circuit is designed lies in lining up the arrangement of the aerial data, have adopted one pair of ports ram to cooperate with the counter and realize the lining up of the data, on the other hand, interface focal point that circuit design transmission of data, part this finish mainly and interface of linkport of dsp, make data transmisst to dsp processor at a high speed, go on follow - up punish

    一方面，介面電路設計的重點在於對天線數據的整理排隊，採用了雙埠ram配合計數器實現數據的排隊，另一方面，介面電路設計的重點是數據的傳輸，這部分主要完成和dsp的linkport的介面，使數據高速傳給dsp處理器，進行后續處理。這個項目按照自上而下的設計流程，從系統劃分、編寫代碼、 rtl模擬、綜合、布局布線，到fpga實現。
  2. D / a conversion chip and isolation amplifiers are used to obtain the comparative levels required by isolation channels, which could be set with actual requirement ; it can enhance flexibility of the module. otherwise, four - channel isolation signal sources are exported using d / a conversion chip and isolation amplifiers as well

    另外還利用d / a轉換晶元和隔離運算放大器輸出四路隔離信號源，該隔離信號源能與隔離比較電平通過繼電器進行程式控制切換，這樣擴展了該計數器模塊的功能。
  3. The thesis discussed a parameter extraction program for the mosfet level1 model. in the analysis and design of circuit, at first, the thesis described the system function of the new dc - dc switching converter. then several sub - circuits of converter ic such as oscillator, over - temperature shutdown circuit, auto - restart counter circuit and control circuit were completely discussed

    在電路設計中，本文首先分析了開關電源電路的基本拓撲結構和psm調制模式，接著對開關電源變換器進行了系統的原理分析並設計了總體框圖，然後詳細設計了振蕩器電路，熱保護電路，自動重啟計數器電路和主控門邏輯等子電路並進行了功能模擬。
  4. Due to the low mechanical efficiency and long circulating period of the down - charging system of cold bed in bar production line, this paper puts forward the improving project, which adopts ethernet supplemented by dp network, applies the fm350 - 2 advanced counter and suitable maths model and combines the technique of the transducer and hydraulic pressure drive control to realize auto - control

    摘要針對棒材生產線上冷床下卸鋼系統機械效率低、運行周期長，不能適應快節奏生產的現狀，採用以工業以太網為主、 dp網為輔的網路通訊，應用西門子fm350 - 2高速計數器，通過有效的數學計算模型，結合變頻器和液壓傳動控制技術，實現網路自動化控制。
  5. The simulation shows that both pulse - swallowing counter and d / a converter ' s working frequency reach 330mhz

    模擬結果顯示，吞脈沖計數器及d a轉換器等器件的工作頻率均達到了330mhz 。
  6. Relay transistor output lcd display 8 function key built - in

    具有高速計數器外部中斷時間中斷模擬輸入輸出萬年歷rtc等功能。
  7. There is difference frequency measurement requirement for every part of pid regulating, difference between dynamic quality and static quality in response time and accuracy. according to these, it use the interrupt functions and high - speed counter of the simens s7 - 200 plc cpu226 basic unit and some peripheral circuit to measure frequency ; in software designed, the procedure frame of hydraulic - turbine governor and disperse process of parallel pid are analyzed, an improved pid algorithm is adopted to realize a pid regulation mode with variable structure and parameters ; the mechanical liquid - pressure system of the hydraulic - turbine governor is with electric - hydraulic converter unit of step motor. according to the drive character of five phase of response step motor, a variable frequency regulated voltage driver unit is designed in order to realize interface between plc and driver of step motor

    本文利用s7 - 200plc自身的特點設計了頻率測量單元，根據pid調節各個環節的特點，以及調速器動態特性、靜態特性對頻率測量的實時性和精度要求的不同，利用s7 - 200plc基本單元中內置的高速計數器以及相應的外圍放大整形、分頻電路，實現了水輪發電機組頻率的測量；在軟體上，對微機調速器的整個程序框架、並聯pid的離散化過程進行了分析，選用改進的pid演算法實現了變參數、變結構的pid調節模式；調速器的機械液壓隨動系統具有步進電機電液轉換元件，採用五相反應式步進電機，根據其驅動特性設計了變頻調壓驅動器，實現plc與步進電機驅動器之間數字介面。
  8. The methods of adopting fpga to realize the function of counter, and adopting verilog hdl hardware description language to design every function modules, not only makes the whole design more compact and stable, but also make the alteration of the circuit ’ function merely need to alter the software according to the practical task requires, and needn ’ t alter the hardware connection of the circuit

    在計數器功能的實現上採用fpga （ fieldprogrammablegatearray ） ，利用veriloghdl （ hardwaredescriptionlanguage ）語言編寫了各個功能模塊，不僅使整個設計更加緊湊、穩定且可靠，而且可以根據實際的任務要求，在無需改變硬體電路板的情況下，通過修改硬體描述語言程序，即可修改電路功能。
  9. The whole pwm circuit contains two subcircuit, the front - end is pwm module that make up of the counter that based on nine mosfet true - single - phase - clock d flip - flop ; the back - end is demodulated module, which is consist of a three order chebyshev low - pass filter used trans - conductor capacitor. all the subcircuits are simulated. at last, an approving simulated result of the whole circuit is given too

    在調制部分，利用九管單相時鐘d觸發器構成計數器，並由此組成了脈沖寬度調制電路，同時給出了在典型溫度下的模擬結果;在解調部分，介紹了低通濾波器從無源到有源的設計方法，設計了三階切比雪夫低通跨導電容濾波器，同樣給出了相應的模擬結果;最後，作為將脈沖寬度調制電路和濾波器作為整體電路，以脈沖調頻波為輸入進行了模擬，取得了令人滿意的結果。
  10. 4. demonstrating the structure and design of the counter + delay - line module, by which the pulse waveforms with given pulse delay and pulse width delay can be generated

    4 .設計計數器+延遲線模塊的組成及方案，並據此實現根據觸發信號產生的具有一定脈沖延遲和脈沖寬度的脈沖波形數字信號。
  11. To access the counter in read write mode

    ；若要以讀/寫模式訪問計數器，則為
  12. True to access the counter in read - only mode though the counter itself could be read write

    若要以只讀模式訪問計數器（即使計數器本身可能是可讀/寫的） ，則為
  13. In this paper, the cold die forging technology of the counter gear was analysed, the cold die forging was designed, the blank dimensions and the figure were calculated and choosed, the allowable deformation degree was checked, the equipment for the deformation was selected, the blank treatments before the cold die forging were draw up and the die structure of the cold die forging was designed

    分析了計數器齒輪的冷模鍛工藝，設計了冷模鍛件圖，計算及選用了毛坯尺寸及形狀，驗算了許可變形程度，選擇了變形用的設備，擬制了冷模鍛前的毛坯處理及設計了冷模鍛模具結構。
  14. Abstract : in this paper, the cold die forging technology of the counter gear was analysed, the cold die forging was designed, the blank dimensions and the figure were calculated and choosed, the allowable deformation degree was checked, the equipment for the deformation was selected, the blank treatments before the cold die forging were draw up and the die structure of the cold die forging was designed

    文摘:分析了計數器齒輪的冷模鍛工藝，設計了冷模鍛件圖，計算及選用了毛坯尺寸及形狀，驗算了許可變形程度，選擇了變形用的設備，擬制了冷模鍛前的毛坯處理及設計了冷模鍛模具結構。
  15. Advanced fpga technology is introduced to improve the integration of digital circuits, and all digital circuits in the original module are integrated in the fpga chips, which could not only reduce the cost, but also improve the reliability and measurement precision of the circuits. high speed digital signal processor ( dsp ) is selected as the coprocessor instead of scm ; it can receive all kinds of commands sent from vxi, analyze and execute the commands, harmonize each section of the module and process the data. higher - conversion - speed comparator chip is adopted to convert the input signals being measured into square waveform signals which could be identified by fpga chip ; it can expand the measurement range of frequency dramatically

    本文在原有vxi總線四通道計數器模塊的設計基礎上，通過對原模塊缺陷的分析，採用一些新的技術和新的電子器件來重新設計該計數器模塊:採用最新的fpga技術來提高數字電路的集成度，將原模塊中的所有數字電路全部集成在fpga晶元中，這樣不僅能節約成本，還能提高電路的可靠性和測量精度;採用高速的數字信號處理器（ dsp ）取代原有的單片機作為協處理器，來接收vxi發來的各種命令，分析命令、執行命令、協調模塊各部分的工作以及對數據的處理;採用轉換速率更高的比較器晶元將輸入的被測信號轉換為fpga晶元能夠識別的方波信號，能極大提高測量頻率的范圍;採用d / a轉換晶元和隔離運算放大器得到隔離通道所需的比較電平，該比較電平值能夠根據實際需求進行設置，能增強模塊的使用靈活性。
  16. Digital feedback twice sampling a / d converter is based on common accurate dual integral a / d converter. during the second sampling, through the control logic, programmable counters and switch control, realize digital feedback and substitute primary analogue feedback realized by high accuracy d / a converter

    在第二次采樣中，通過控制邏輯、可編程計數器和開關控制來實現數字反饋，以取代原有的兩次采樣a / d轉換器中通過高準確度d / a轉換器所實現的模擬反饋。
  17. On the basis of the analyses on the development status of pxi - bus universal counter and the requests of the users, the whole scheme is determined in this thesis

    本文在參閱了大量技術參考文獻的基礎上，通過對國內外pxi計數器發展情況的調研及對用戶需求的分析，確定了模塊的總體方案。
  18. We also magnify the signal with new ic amplifier, deduct yawp counters, design system to desl with data, total system is control by singlechip and can count in fastness time range and deal with data

    用max4416放大器件作為前置放大器，用max900系列比較器件作成窗口比較器，用高速器件74ls393兩片作成16位的計數器，用單片機89c51讀取數據，並處理后顯示在液晶顯示模塊上。
  19. In the scheme, not only the rtlinux ' s double kernel structure and its virtual interrupt are adopted, which make the standard linux process as the lowest priority one in the real - time kernel, but also the 8254 is set to work in the one - shot model by using the kurt ' s utime package, which improves the clock frequency of the os and reduces the cpu ' s extra burden

    這種新的實時化方案利用了rtlinux的雙內核體系結構和中斷虛擬機技術，將標準linux進程作為實時內核的一個優先級最低的任務進行調度；同時還利用了kurt中utime軟體包將定時/計數器8254置為one - shot工作模式，從而既提高了操作系統的時鐘頻率，又解決了cpu額外負擔過重的問題。
  20. A goal - based load pattern resembles the step pattern but adjusts the user load based on performance counter thresholds versus periodic user load adjustments. goal based loads are useful for a variety of different purposes

    基於目標的負載模式與單步模式相似，但它基於相對于定期用戶負載調整的性能計數器閾值調整用戶負載。
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