浮點硬體 的英文怎麼說

中文拼音 [fúdiǎnyìngtǐ]
浮點硬體 英文
floating point hardware
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 浮點 : [計算機] floating decimal; floating point
  • 硬體 : hardware
  1. Firstly, the dissertation expatiate the develop of epu ' s software and hardware. the hardware is a data acquisition system based on the ps multiprocessor architecture

    硬體是以主從式多處理器結構為核心數據採集系統，主機和從機分別採用ti公司浮點dsp晶元7ms320c31pq和定點dsp晶元tms320f240 。
  2. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  3. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  4. School areas are too large and the schoolyards and green spaces are too small ; classroom construction is not up to national standards ; and classrooms contain too many students. furthermore, the school desks and chairs often are not compatible ; and books, instruments and sports equipment are far from enough. there is a gap between software and hardware in the configuration of audio - visual aids ; and the coefficient of the utilization of existing equipment is low and ineffective

    通過研究發現，西峰市普通完全中學目前存在著布點不合理，學校規模過大，校園及綠化面積偏小，教室建築規范性差，室內學生容納過量，課桌椅不配套，圖書、儀器、體育器材嚴重不足，電化教學設備軟硬體配置比例失調，現有教學設備利用率低、效益差，學校管理者教學設施建設中作風浮夸等問題。
  5. Different with traditional microprocessor which solves floating - point normalization with soft ware, the project implemented floating - point normalization with hard ware. the research focused on the architecture of microprocessor mainly

    因本課題意在實現微處理器的基本結構，並未涉及到編譯器，因此在對微處理器的浮點處理單元的規格化演算法進行深入分析的基礎上提出了用硬體實現浮點單元規格化的方法。
  6. A number of challenges needed to be met to design and implement a jpeg coding in hardware rather than in software running on a microprocessor. jpeg coding normally requires many floating - point multiplication calculations

    Jpeg需要進行大量的浮點乘法運算，但用硬體實現乘法運算會佔用比實現加法運算多得多的晶元資源。
  7. The rs64 family leaves things like branch prediction, exceptional floating - point powers, and hardware prefetch to its power3 cousin and focuses instead on exceptional integer performance and large, sophisticated on - and off - chip caches

    Rs64系列將諸如分支預測、浮點處理以及硬體預取之類的問題留給其兄弟power3晶元來解決，自己則專注于整數運算性能和大型復雜的片上、片外緩存的處理。
  8. According to the feature of vibration isolation system, referring to the principle of the magnetic suspension, a electromagnetism actuator is designed for the active vibration isolation system application and also a power amplification circuit is designed to adapted to it

    針對隔振系統的特點，參考磁懸浮的原理，設計了適合主動隔振系統應用的電磁作動器，並設計了與之配套的功率放大電路，還對其他系統必需的硬體進行了選型。
  9. The chip area and power savings of not implementing floating - point in hardware can be critical in embedded microprocessors

    在嵌入式微處理器中，硬體中省去浮點（支持）而為實現帶來的晶元面積和功率的減少是至關重要的。
  10. In terms of the key to the control system, the hardware system is designed including main winding converter, radial force winding converter, driving circuit, snubbers, protect circuits and signal regulator

    在分析本系統控制要點的基礎上，設計製作了無軸承開關磁阻發電系統硬體部分，為實現無軸承開關磁阻發電機懸浮控制提供了可靠的實驗條件。
  11. Note that embedded microprocessors are frequently implemented without direct hardware support for the powerpc floating - point instruction set, or only provide an interface to attach floating - point hardware

    注意，嵌入式微處理器實現時經常不提供對浮點指令集的直接硬體支持，或者只是提供一個附加浮點硬體的介面。
  12. Moreover, high precise floating number and skill of floating point calculation are not needed

    它速度快、硬體兼容性良好、可調，且不需要較高的精確浮點數或是浮點運算技巧。
  13. In the last chapter, implementing the location algorithm by dsp and fpga is the main work. the programs of location and fitting of flight path are designed in visualdsp + + environment, the interface control module with cpci is implemented by fpga

    本論文選用adi公司的高性能浮點處理器adsp - ts101實現無源定位硬體電路模塊，並利用其軟體開發平臺visualdsp + +開發了相關的定位演算法，用fpga編程實現了dsp處理模塊與主機cpci介面相連。
  14. To decrease the area of the chip, resource sharing, which is a synthesized optimized method of eda tools, was used in the project. the code was verified in fpga soft ware environment. synthesized netlists based on fpga and asic were given in the paper for future work

    本課題所設計的微處理器的整數單元和浮點單元均採用硬體描述語言vhdl進行建模，為降低晶元面積，將資源共享這一eda工具的綜合優化方法應用於設計中，並在現有條件下進行了簡單的fpga驗證，考慮到今後的asic設計，本文給出了基於fpga和基於asic的兩種綜合網表。
  15. This hardware can complete 120 million times float operation in one second. the rate of a / d conversion is up to 500ksps and the precision is up to 16 bits

    該硬體可以實現每秒120兆次浮點運算，採用一片ltc1608進行a d轉換，片內自帶采樣保持器、解析度為16位、轉換率為500ksps 。
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