環路鎖相 的英文怎麼說

中文拼音 [huánlùsuǒxiāng]
環路鎖相 英文
looped phase locking
  • 環 : Ⅰ名詞1 （環子） ring; hoop 2 （環節） link 3 （姓氏） a surname Ⅱ動詞（圍繞） surround; encircle;...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 相 : 相Ⅰ名詞1 （相貌; 外貌） looks; appearance 2 （坐、立等的姿態） bearing; posture 3 [物理學] （相位...
  1. Contrapose to the instability of the third - order charge - pump pll system, the loop optimization method is employed in system level design to decide the bandwidth and phase margin, therefore the loop bandwidth locates at the maximum phase margin to guarantee the stability of the system. according to tsmc 0. 35 m sige bicmos model, the sub - circuits in the designed pll and the whole system are simulated and verified by the cadence spectre

    5 .根據tsmc0 . 35 msigebicmos工藝模型，利用cadencespectre模擬軟體對所設計的電荷泵鎖相環路中各個模塊及整個系統進行了模擬模擬，模擬結果顯示，在1 . 5v電源電壓下，頻率為200mhz的參考輸入信號，輸出中心頻率為800mhz ，分頻電路採用4分頻，環路帶寬為10mhz ，捕獲時間大約為0 . 92 s ，功耗大約為15mw ，達到了設計指標。
  2. In the next place, by studying the change of the resonant frequency of the whole system, this paper designs the circuit to track the resonant frequency of the system by cd4046 mainly. at the same time, in order to improve the efficiency and get better dynamic capability of the converter, we choose pll and fuzzy control after comparing the pll circuit, fuzzy circuit and pll ? fuzzy control circuit. in the end, this paper brings forward the control blue print to realize the drive control circuit of the high frequency converter, using the dsp chip as the key part to realize four routes of pwm drive pulses with dead band of the control system

    其次，通過對整個系統諧振頻率變化的分析和研究，設計了以鎖相環cd4046為核心的鎖相環控制電路，同時，在綜合比較鎖相環控制、模糊控制以及模糊控制和鎖相環復合控制三種控制演算法的基礎上，進行了系統模擬，得出採用復合控制可使跟蹤電路既具有鎖相環路較好的穩態性能，又擁有模糊控制較好的動態性能，系統魯棒性能好，同時也提高了逆變器的效率。
  3. Monitor apparatus can measure valid value of three phase voltage and current, power factor, three phase disequilibrium, instant flecker of short time and harmonic without twenty, degree and harmonic distortion total. the paper are laid on the following. ( 1 ) master plan and function of circuit, ( 2 ) hardware design including circuit and principle of a / d conversion, phase lock, liquid crystal display and keystroke and so on, ( 3 ) design of system software including digital filtering, fft, a / d conversion and monitor interface of pc, ( 4 ) system test

    監測儀能夠完成包括三相電壓、三相電流的有效值、功率因數、三相不平衡、電壓短期閃變、以及20次內的諧波、諧波相位、諧波失真總量等的測量。論文重點介紹了以下幾部分： （ 1 ）電路的總體設計和功能； （ 2 ）硬體設計，包括a d轉換、鎖相環、液晶顯示和按鍵輸入等原理和電路。 （ 3 ）系統軟體設計，包括a d轉換、 fft 、數字濾波等程序的原理和演算法以及上位機監控界面的設計； （ 4 ）系統測試。
  4. Design of hardware consists of three pll loops, micro wave sample mixer, fractional - n frequency divider

    硬體電路包括三個鎖相環，取樣混頻器，分數分頻器的設計等。
  5. In this thesis, firstly, we put forward a new algorithm of the synchronization of carrier reference phase, that is to use the curve synthesizing with the general digital carrier phase looper to have an estimation on carrier frequency within 10 ms so as to meet the need of meteor burst communication. we have done some simulations to get the performance of carrier frequency estimation using two modulation modes ( 16qam and 4 - qpsk ), and had some test on the carrier phase looper in conditions when using different baud rate transmission and when the baud tuning have windage

    我們對兩種正交調制方式（ 16qam和4 - qpsk ）進行了模擬工作並給出了模擬結果，同時討論了碼元同步定時誤差對鎖相環路工作的影響並根據流星通信中使用變速率傳輸時鎖相環路的載波同步性能進行了測試；然後在基於軟體無線電思想的數字處理平臺（該數字處理平臺實現了中頻數字化）上用dsp軟體完成了載波的相位跟蹤。
  6. In this paper, a clock recovery system that based on phase control technology is studied

    本文設計的鎖相環路是基於相位控制技術的時鐘恢復系統。
  7. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  8. The carrier wave is modulated directly by the baseband signal at several frequency point in l band and s band. firstly, this paper clarifies the theory of i / q modulation, elaborates evm and acpl, and analyzes the effect of amplitude and phase unbalance and dc offset on evm. secondly we review the basic principle of phase locked loop and it ’ s composing parts, including the basic conception and design method of pll frequency synthesizer, especially introduce the charge pump pll frequency synthesizer in detail

    首先，在闡述i / q正交調制基本原理的基礎上，通過對誤差矢量和鄰近通道功率泄漏的詳細分析，定性、定量地討論了各種非理想電路因素（如相位不平衡、幅度不平衡、直流偏差等）對調制器性能的影響;其次，介紹了鎖相環的工作原理和基本組成部分，包括鎖相環的設計和環路濾波器的設計，特別詳述了電荷泵鎖相頻率源;第三，介紹了採用直接調制技術模擬衛星信號的射頻前端的設計;最後，對整個直接射頻調制系統進行測試，結果基本上達到了課題要求。
  9. This paper has launched exhaustive analysis and study to every module of pll and its key part ( vco ) is also improved. the history of phase - locked technology and the actuality of research on it are introduced. and then beginning with the fundamental principles of a phase - locked system, we build the mathematical model based on the architecture of the traditional analog pll, and afterwards investigate some of its characters such as tracking, acquisition, noising, and stability

    本文在對鎖相技術的發展歷史和研究現狀調查研究的基礎上，從鎖相系統的工作原理入手，分析了鎖相環的數學模型，並以此為出發點對其跟蹤性能、捕獲性能、穩定性及噪聲性能等性能進行了較為深入的研究，對環路的各項參數指標進行了詳細的推導，得出了鎖相環數理分析的普遍結論。
  10. 3. with comprehensive improvement of transponder including structural adjustment to lna ; optimization of ( phase locked loop ) pll filter ; structural adjustment to the transmitter and phase error adjustment to the intermediate frequency demodulation circuit, we have successfully enhanced sensitivity, expanded dynamic range, increased transmitting power and improved the spectrum purity ; decreased capture time for pll ; improved the signal quality after demodulation ; reduced its volume and power consumption. 4

    3 、對通信機的全面改進，包括lna結構的調整、鎖相環環路濾波器的優化、發射部分結構的調整以及中頻解調電路的相差調整，提高了系統的接收靈敏度、改善了本振的頻譜純度、減少了鎖相環的鎖定時間、使中頻解調后的信號質量大為提高，同時還減少了體積、節約了系統的功耗。
  11. Pll frequency synthesizer is increasingly used in microprocessor systems and communication. with the development of integrated circuits and the emergence of soc ( system on a chip ) technology, it has been a fundamental and very important module in analog and mixed - signal integrated circuits

    鎖相環頻率合成器現在日益廣泛地應用於通訊、微處理器系統中，並且隨著集成電路的發展以及soc技術的出現，其已經成為超大規模集成電路中不可或缺的模塊。
  12. For digital audio encoding and decoding modules, delta - sigma modulation is introduced and audio data, preambles with accessorial data are multiplexed according to the digital audio interface standard ; for carrier wave, pll frequency synthesizer is used ; for frequency modulation, voltage control oscillator is taken ; for demodulation, pll frequency discrimination is adopted

    調制方式，並按照數字音頻介面標準對音頻數據、同步字和附加信息進行通道復用;對于載波信號，採取鎖相環頻率合成技術手段;對于頻率調制，採用壓控振蕩器;對于解調電路，採取鎖相環鑒頻電路。
  13. Critical circuits in developing this board, such as tht modulation circuit, demodulation circuit, pll and filter, were analyzed in detail. parameters adopted in these circuits were also calculated. based on all that mentioned above, a rf board was implemented and related tests and experiments were successfully done as well

    本文主要對cdpd移動終端數據機的硬體開發中的關鍵部分?高頻部分電路進行了研究，論文在cdpdv1 . 1規范的基礎上，提出了射頻部分電路的實現方案，選擇了合適的核心晶元，並對電路中的調制解調電路、鎖相環、濾波器等關鍵模塊進行了較為詳細的分析，對電路中的有關參數進行了計算。
  14. Detail specification for electronic component. semiconductor integrated circuit - type cd 7343 gs phaselocked loop fm stereo decoder

    電子元器件詳細規范.半導體集成電路cd 7343 gs型鎖相環調頻立體聲解碼器
  15. Since commercial pll ic came out, phase - locked - loop frequency synthesis has become widely accepted. but when narrow frequency - step is required, the loop bandwidth has to decrease while cannot meet the demand of frequency - hopping speed

    數字鎖相集成器件出現以來，鎖相式頻率合成器得到迅速發展，但是當需要窄頻率步進時，環路帶寬需要降低，致使鎖定時間變長，不能滿足快速跳頻的要求。
  16. With the phase - noise model of the phase loked loop ( pll ) and the analysis of spur characteristic of fractional - n frequency synthesizer using - ? modulating technology, the scheme of pll with mixer + quadrupler is confirmed as a result

    文中，通過建立鎖相環路的相位噪聲模型，並分析了使用- ?調制技術的分數頻率綜合器的雜散性能，以此二者為理論依據完成了毫米波頻率源合成器的基本方案? ?鎖相混頻環+倍頻器方案。
  17. The basic operation principle of phase - locked frequency synthesizer and the type of circuits are expatiated systematicly in this paper. the principle of operation on sampling phase detector and some characteristics including the linear tracking and phase noise in phase loop circuits are analyzed deeply. the research is emphased on the theory and design method of circuits in the sampling phase - locked frequency synthesizer. then, the expansion capturing circuit is analyzed and designed for better performance of capturing loop circuits. at last, the loop filter is also analyzed and contrived taking account of effection of additional phase shift by the sampling - holder. the general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product

    本文系統的闡述了鎖相頻率合成器的基本工作原理及電路類型；較深入地分析了取樣鑒相工作原理及電路、鎖相環路的線性跟蹤特性和相位噪聲特性；重點對取樣鎖相頻率合成器電路理論和設計方法進行了研究；為了改善環路的捕獲性能，對擴捕電路進行了分析和設計，並用wewb32軟體對電路進行了模擬；考慮到取樣保持器的附加相移影響，對環路濾波器進行了分析和設計。
  18. And the new circuit structure for improving the locking range, that is, injection - locked phase - locked loop circuit ( ilpll ) is introduced into the millimeter wave circuit

    在此基礎上，結合注入鎖定和環路鎖相原理，在毫米波頻率源中引入了一種新型的展寬帶寬的電路結構環路注入鎖定鎖相電路（ ilpll ） 。
  19. Photoelectric detecting circuit is constituted of four parts, i / v conversion, lock - in amplifier, low - pass filter and operation

    光電檢測電路由四部分組成，分別是i / v轉換環節、鎖相放大環節、低通濾波環節、運算環節。
  20. Thus, the better phase noise can be obtained by adjusting the loop wave filtering. through experimental verification, the locking range of the designed ka band ilpll circuit is 2. 5 times to 9 times widened and the phase noise, compared to that without feedback loop, is reduced by 4dbc @ 1khz and the noise can be reduced by adjusting the loop wave filtering and

    經過實驗驗證，設計的ka波段ilpll電路的鎖定帶寬拓展了2 . 5倍以上，最大處達到9倍左右;相噪與開環注鎖相比降低了4dbc @ 1khz ，且可以通過調節環路濾波和注入功率來降低噪聲。
分享友人
分享到 Line

分享到臉書