硬區緩沖 的英文怎麼說

中文拼音 [yìnghuǎnchōng]
硬區緩沖 英文
relief of hard area
  • : 形容詞1 (堅硬) hard; stiff; tough 2 (剛強; 堅定; 強硬) strong; firm; tough; obstinate 3 (勉...
  • : 區名詞(姓氏) a surname
  • : Ⅰ形容詞1 (遲; 慢) slow; unhurried 2 (緩和; 不緊張) not tense; relaxed Ⅱ動詞1 (延緩; 推遲) d...
  1. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼; fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制;視頻數據幀存模塊為大量高速的視頻數據提供;基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號; d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用: i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  2. The hardware designing include the interface with engine controller, such as d / a conversion. we chose the ad75089 which was produced by ad corp. this is a parallel port digital to analog conversion, and i give the presentation about its structure and connection scheme. in order to resolve the contradiction between faster computation and slower display, a buffer storage also needed

    第二部分詳細陳述了高速數據傳輸卡的軟、體設計過程,體設計包括dsp與pci總線的介面、 dsp與外部控制器的介面、以及電路卡上的擴展數據的設計,並使用專門的工具軟體protel繪出全部體電路的設計原理圖。
  3. The main research issues consist of following aspects : 1. based on non - real - time ethernet and windows2000, we research how to meet the real - time requirement for hsm working procedure, via using shared data buffer to resolve the conflict between high - speed data acquisition and low - speed data process, then combine hsm features, correctly set priority among processes and threads, and compositively use software and hardware technical

    主要內容為: 1 .詳細研究了在採用非實時的以太網( ethernet )和windows2000操作系統基礎上,如何通過使用共享數據、解決高速數據採集與低速數據處理分析的矛盾,結合熱連軋的工藝特點,合理設置進、線程優先級,綜合運用軟、體措施滿足象熱連軋生產過程這樣的快速過程的實時性要求。
  4. Some hardware tests the compatibility of the depth stencil buffer with the color buffer

    某些體可測試深度模具與顏色的兼容性。
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