硬布線 的英文怎麼說
中文拼音 [yìngbùxiàn]
硬布線
英文
hard wired-
Usage and feature : clap many selected layers of sisal hemp cloth, made from pure spiral cotton thread, treated with resin dipping and make the body hardy and the cutting more powerful, more endurant, suited for stainless steel and disware grind
用途與特徵:選用多層劍麻布交叉疊放，再用純棉線螺旋車制而成，再用樹脂浸漬處理，使輪身堅硬，更具切削力，耐磨，適合於不銹鋼、餐具研磨。According to the research, the major work done is as following : < 1 > analyzes the symmetric - key encryption algorithm des and dissymmetric - key encryption algorithm rsa, and makes them easy to realize in hardware. < 2 > according to the algorithms and the thought of reconfigurable computing, the dissertation accomplishes the design of 64 - bit des system architecture and the design of 256 - bit ~ 1024 - bit rsa system architecture. < 3 > using the top - down high level design methodology and the hdl language, accomplishes the description of the des / rsa designs, the simulation and the synthesis
本論文主要的研究工作： < 1 >對現有的對稱加密演算法des演算法和非對稱加密演算法rsa演算法進行分析，使其易用硬體實現； < 2 >基於可重構思想和特點，完成64位des演算法和256位1024位模長rsa演算法的可重構硬體的設計； < 3 >採用自頂向下的設計方法，利用hdl語言對des / rsa設計進行功能描述，並完成軟體模擬，綜合和布線； < 4 >在可重構計算驗證平臺上進行演算法驗證，並對設計的可重構和設計的進一步優化進行討論。Then the general platform hardware will be cut out and integrated, all of the circuits and the pcb will be designed and realized. the design process of pcb needs to follow the idea of high speed circuit layout, otherwise the pcb can ’ t work any more
之後，在此平臺上進行硬體的裁剪與集成，設計和實現無線接入系統的硬體電路，最後製作出pcb ，其中pcb的製作要依據高速pcb的布局布線的思想進行，才能保證系統正常工作。The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block
設計的riscmcu採用14位字長指令總線和8位字長數據總線分離的harvard結構和二級指令流水設計，並使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執行效率。The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl
該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。Describes the design and realization of partial run - time reconfigurable fpga in detail. in order to reduce the affect of the reconfiguration time on system execution time, mostly static circuit design method in logical design stage and incremental routing method in component implementation stage are proposed. the fft parallel processing algorithm is examined through vvp platform
本章詳細闡述了基於vvp平臺的多sharc功能插板的具體硬體實現，以動態重構fpga設計為核心，論述了局部動態重構fpga設計流程和方法，提出了極大靜態電路邏輯設計方法和遞增式布線方法，以達到減小動態重配置時間，提高系統運行效率的目的。There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally
首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。Rigid steel conduits
硬布線鋼管The resulting “ program ” is in the form of hardware and is termed a hardwired program
編程的結果是以硬體形式實現，也可以被稱為硬布線程序。The thesis introduces the architecture, datapath, hardwire control of the soft core, and introduces the verification of the soft core. mcu is the heart of the embeded system
本文介紹了hgd08r01軟核的risc體系結構、數據通道設計、時序設計以及硬布線控制設計等，同時還介紹了改軟核的驗證流程與方法。The soft core design of 16 - bit microprocessor realizes all the required functions, which are verified with fpga test bench ( for example, the controller is implemented with hard - wired logic ). with the design of the microprocessor some design ideas are implemented and some valuable experiences are accumulated
本文是對微處理器設計中一些設計思想的實現（如採用硬布線邏輯來實現微處理器控制器） ，並積累了一些寶貴的設計經驗，可為其他設計提供有益的參考。For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively
摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function
本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。For example, a conventional wired system would have required up to 30 control cabinets but this will be reduced to just five with the simplified wiring and reduced hardware required by the foundation fieldbus network
舉例來說，傳統的有線系統將需要多達30個控制櫃，但這樣將減少到只有5個，並簡化了布線和減少了基金會現場總線網路所需的硬體。Then has analysed function 、 port joining 、 inside structure of every module, etc. in detail. using hardware description language to program for function implementation, after function simulation 、 synthesis 、 place and route 、 timing simulation and download, the design is implemented in the spartan 3 serial xc3s400 - 4pq208 chips of xilinx. all procedure of design is worked under the ise 6. 2 integrated environment
接著詳細分析了各模塊的功能、埠連接、內部結構等，並利用硬體描述語言編寫源代碼實現各模塊功能，經過功能模擬、綜合、布局布線、時序模擬、下載等一系列步驟，最終在xilinx的spartan3系列xc3s400 - 4pq208晶元上實現。Its additive device performance means full bandwidth to each drive. sata cabling provides scalability, hot - plug connections mean quick drive replacement, and cyclical redundancy checking builds toughness
Sata布線提供了可擴展性熱插撥連接實現了硬盤的快速更換而循環冗餘碼校驗crc則保證了產品的牢固。Taking library of jiujiang university as example, the paper gives a brief description of some questions in constructing process of network upgrading, such as plan of line distribution, equipment of network hardware and assisting equipment
摘要以九江學院圖書館?例，簡述升級千兆網路所涉及布線方案、網路硬體設備及輔助設備等幾個方面的改造構建過程。This dissertation combines hardware descriptive language, production line transfer technology, ping - pang memory technology and fpga wiring optimization technology to implement data branch and treating
本文綜合運用硬體描述語言、流水線傳輸技術、乒乓存儲技術、 fpga布線優化技術實現了採集卡的數據分流及處理。This dissertation finishes the design of pci bus target controller, with vhdl description of register transfers level. and it has also completed the function simulation as well as timing simulation after placing & routing. a fpga on pcb board is designed to test the target controller and the result of test meets basal function demand
本論文完成了pci總線目標設備控制器的設計，採用vhdl對其進行了rtl級的描述，並且通過編寫測試激勵程序完成了功能模擬，以及布局布線后的時序模擬，通過fpga在pcb實驗板上進行硬體模擬，證明所實現的pci目標設備控制器符合基本功能要求。Telecommunication generic cabling system for building part 3 : connecting hardware requirements for generic cabling
大樓通信綜合布線系統第3部分：綜合布線用連接硬體技術要求分享友人