硬體描述語言 的英文怎麼說

中文拼音 [yìngtǐmiáoshùyǔyán]
硬體描述語言 英文
hdl hardware description language
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 描 : 動詞1. （照底樣畫） copy; depict; trace 2. （在原來顏色淡或需改正之處重復塗抹） retouch; touch up
  • 述 : Ⅰ動詞（陳說; 敘述） state; relate; narrate Ⅱ名詞（姓氏） a surname
  • 語 : 語動詞[書面語] （告訴） tell; inform
  • 言 : Ⅰ名詞1. （話） speech; word 2. （漢語的一個字） character; word 3. （姓氏） a surname Ⅱ動詞（說） say; talk; speak
  • 硬體 : hardware
  • 描述 : describe; represent
  • 語言 : language
  1. The circuits driving the ccd and processing the video signal are implemented by means of cpld ( complex programmable logic device ) and hdl ( hardvvare description language ). the solution to solve the problem of multi - level logical competitive risks that occur in cpld circuits frequently was provided in details in the thesis

    Ccd的驅動電路和視頻信號處理電路採用cpld （可編程邏輯器件）和hdl （硬體描述語言）實現，文章對cpld電路中容易出現的多級邏輯冒險競爭情況作了專門的敘述和提出相應的解決方法。
  2. Digital image processing consume a large amount of memory and time commonly. basing on the advantage of fpga, the paper design harware module by hdl ( hardware language ), i. e., some function is achieved by les ( logic element ) of the fpga. the real - time of digital image processing is achieved by this. the sample and display of digital image is the important part. so, the paper mainly design the sample and desplay module. the sample card is designed and it ’ s word mode is configured according china ’ s cvbs ( composite video bar signal ). for acquiring the image and storing it correctly to sram, the paper design the sample - control module. the sample module can work correctly using least time. the reliability and real - time achieve the reference. according the vga principle and scheduling of the ths8134, the paper design a vga - control module by hdl. firstly, the control signal is synthesized secondly, the horirontal and vertical synchronization signals is synthesized according to the vga interface standard

    圖像處理的特點是處理的數據量大，處理非常耗時，為實現數字圖像的實時處理，本文研究了在fpga上用硬體描述語言實現功能模塊的方法，通過功能模塊的硬體化，解決了視頻圖像處理的速度問題。圖像數據的正確採集和顯示輸出是其中的兩個重要的模塊，因此，本文主要完成了圖像數據的採集和顯示輸出的設計。本文設計了採集卡，並要對其工作模式進行了配置和編寫了採集控制模塊，在採集控制模塊的控制下，將數字圖像數據正確無誤的存儲到了sram中。
  3. Thi s dissertation first describes syntax, semanteme and method of modeling hardware of veri1og hdl and vhdl in detai1 so that strong abi1 ity of designing and simu1ating waveform is represented in hardware circuits

    本文首先對兩種硬體描述語言veriloghdl和vhdl在語義、語法及硬體建模方法進行了詳細的描述，說明它們在硬體電路波形表示方面有較強的設計與模擬能力。
  4. At last the algorithm of ddmf is achieved by the investigation tool of altera company ? quartus ii and the vhdl language, and its ip core is also achieved which is used not only in the satellite navigation position system, but also in the long pn code dsss system. ddmf investigated in the dissertation gives a good way to design the rapid pn code acquisition in the beidou project, and the technology has the definite theory and practice significance

    此外還應用altera公司的最新的fpga開發工具quartusiiv5 . 1 ，採用了國際標準的硬體描述語言? vhdl語言，對數字差動匹配濾波器和傳統匹配濾波器演算法予以實現，開發了該演算法的軟ip核，可以對所應用的擴頻碼長度， a / d采樣后的數據量化階數，所用擴頻碼等可進行隨意改寫。
  5. It is an important character that using hdl describes function and behavior of logic device or system hardware

    使用硬體設計語言來描述邏輯器件及系統硬體的功能和行為是硬體描述語言編程設計方法的一個重要特徵。
  6. Because period narrow band signals are the main part of background noises, this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises

    3 ）在現場環境中，背景干擾主要是周期性的窄帶，本文利用硬體描述語言（ vhdl ）設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能幹凈的信號。
  7. Main characteristics include object - oriented language core, interfaces between vera core and hdl implemented by interface definition and port variables, complex concurrency control implemented by programming construction ( fork / join ) and data structures ( event, mailbox and semaphore, etc ). all these help vera successfully model hardware properties

    主要的特點是：面向對象的語言內核；通過界面定義和埠變量等實現了vera語言內核和硬體描述語言的介面；通過編程結構fork join和數據結構（事件、郵箱和旗語）來實現復雜的并行控制，實現對硬體特點的模擬。
  8. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。
  9. The whole correlation - inheritance coding circuit system is designed, simulated and verified in verilog hdl on the candence systems

    採用了硬體描述語言verilog對整個相關繼承矢量量化圖像編碼電路系統在cadence系統上進行了西安理工大學碩士論文設計、模擬及時序驗證。
  10. Integrated circuit computer hardware description language verilog

    集成電路計算機硬體描述語言verilog
  11. There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally

    首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。
  12. As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost

    所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。
  13. The methods of adopting fpga to realize the function of counter, and adopting verilog hdl hardware description language to design every function modules, not only makes the whole design more compact and stable, but also make the alteration of the circuit ’ function merely need to alter the software according to the practical task requires, and needn ’ t alter the hardware connection of the circuit

    在計數器功能的實現上採用fpga （ fieldprogrammablegatearray ） ，利用veriloghdl （ hardwaredescriptionlanguage ）語言編寫了各個功能模塊，不僅使整個設計更加緊湊、穩定且可靠，而且可以根據實際的任務要求，在無需改變硬體電路板的情況下，通過修改硬體描述語言程序，即可修改電路功能。
  14. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  15. Then we explicate the hardware design in details, including implementing ad convert, extending multiple serial communications and external memory, and using cpld do some logic controls. thereby we implement abundance simulation interface, flexible digital interface and serial communication interface. at last we describe the software design, including software design of cpld basing on vhdl and software design of dsp

    本文首先介紹飛行模擬訓練系統的主要組成；接著說明飛控計算機整體系統方案的設計；然後詳細說明飛控計算機硬體平臺的設計，包括ad轉換、多串口通信、外部存儲器的擴展以及採用可編程邏輯器件cpld實現電路的邏輯控制等幾部分，體現了系統豐富的模擬介面、方便靈活的數字介面和串列通信介面；最後是軟體部分的編程，包括cpld部分的硬體描述語言程序設計，和dsp部分相關的程序設計。
  16. Becausc of using the advanced dsp, popu1ar high speed pci bus and laxge scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree

    由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得本設計的整個系統具有相當的水平。
  17. Because of using the advanced dsp, popular high speed pci bus and large scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree

    由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得整個系統具有相當高的數據處理能力。
  18. Electronic design hardware description language vhdl

    電子設計硬體描述語言vhdl
  19. Behavioural languages - verilog hardware description language

    行為語言. verilog硬體描述語言
  20. The viterbi decoder with hard decision designed by the paper, is aimed at ( 3, 1, 9 ) convolutional coding. the data rate is 9. 6kbps. the data rate received by the rake receiver is spreaded by 127 - bit spread sequences, added pilot signals and modulated by qpsk

    該課題所設計viterbi譯碼是針對（ 3 ， 1 ， 9 ）卷積碼的硬判決譯碼，數據速率為9 . 6kbps ; rake接收機所接收的數據是擴頻因子為127 、加入導頻且經qpsk調制的擴頻信號，使用verilg硬體描述語言在xilinx公司的ise環境下在用現場可編程門陣列（ fpga ）來實現viterbi譯碼器和rake接=收機的功能。
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