系統總線 的英文怎麼說

中文拼音 [xìtǒngzǒngxiàn]
系統總線 英文
mainbus
  • 系 : 系動詞（打結; 扣） tie; fasten; do up; button up
  • 統 : Ⅰ名詞1 （事物間連續的關系） interconnected system 2 （衣服等的筒狀部分） any tube shaped part of ...
  • 總 : Ⅰ動詞（總括; 匯集） assemble; gather; put together; sum up Ⅱ形容詞1 （全部的; 全面的） general; o...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 系統 : 1. （按一定關系組成的同類事物） system 2. （有條理的;有系統的） systematic
  1. We also take two conclusions by foregoing result : first of all, the system becomes more and more complex, the system data bus utilization copy result, time of system timed and length of the news waiting queue become more and more precise basing on stochastic petri net

    通過結果數據分析、比較，本文得出兩點結論：第一，隨著系統復雜程度的提高，基於隨機petri網的系統總線利用率、系統延時時間、等候消息隊長的模擬結果會越來越精確，這特別適合現代越來越復雜的航空電子綜合系統數據總線的分析。
  2. Autonomous external devices and signals having no bus - compatible signals and no temporal relationship with the system bus signal cannot be connected to the system bus directly

    自治的外部設備和信號由於沒有與總線兼容的信號也沒有與系統總線信號的暫時關系（注：實際上是指沒有暫存器）就無法與系統總線直接相連。
  3. These other boards can ben cpu boards or peripheral boards providing various functions. the vmebus standard originated with the motorola versabus in 1979 which was designed using the then new mc68000 microprocessor

    系統總線吞吐率的優化：其他的晶元組對pci到內存帶寬只能到70mbs ， powerplusii則能達到80mbs而無須消耗額外的cpu資源。
  4. Vmebus boards have data bus sizes of 16, 32, or 64 bits and are designed to be plugged into a backplane that has up to 21 slots for other boards. these other boards can ben cpu boards or peripheral boards providing various functions. the vmebus standard originated with the motorola versabus in 1979 which was designed using the then new mc68000 microprocessor

    性能的提高主要是由於三個方面的改進： 1 .處理器及高速緩存性能的優化2 .降低內存瓶頸：通過對powerplus體系結構的改進，使內存性能提高到582mb s memory read bandwidth和640mb s burst write bandwidth 3 .系統總線吞吐率的優化：其他的晶元組對pci到內存帶寬只能到70mb s ， powerplus ii則能達到80mb s而無須消耗額外的cpu資源。
  5. Its principle is as following : acquire and modulate the analog signals from sensors placed in environments through daq device on real time, then transit the information to computers by pci bus ; in the other hand, noise information tested with sound level meter is passed through interface rs - 232 to computers

    本系統工作原理為：通過多功能數據採集卡採集來自各種傳感器所採集的各檢測對象的模擬信號，對信號進行調理，通過pci系統總線傳遞給計算機；而噪聲則通過聲級計由rs - 232傳入計算機。
  6. The whole part of the data acquisition is build in a computer as two data acquisition cards. they are front card and rear card. the front card composed of four modules. they are : coin circuit module, data flow controller module, sdram array module and system bus interface module. the rear card composed of four odules. they are : asynchronous serial port interface module, adc control odule, ecg signal process module and gate control data produce module

    數據採集模式實現部分的大部分工作是在前面板上完成的，後面板主要是一些外圍電路。前面板採集卡上從物理上來說主要有四塊電路:符合電路，數據流控制器電路， sdram陣列和系統總線介面電路組成。後面板採集卡從總體物理上主要有四塊電路組成: 485串列通信電路， adc控制電路，心電數據處理電路和門控信號產生電路。
  7. Microprocessor system bus i, 8 - bit and 16 - bit data - part 3 : mechanical and pin descriptions for the eurocard configuration with pin and socket indirect connectors

    微處理機系統總線i8位及16位數據第3部分:採用插針和插座連接器
  8. Specification for processor system bus interface eurobus a

    處理器系統總線介面
  9. A information processing - processor system bus interface eurobus a

    信息處理處理機系統總線介面
  10. Microprocessor system bus - 8 - bit and 16 - bit data multibus i. mechanical and pin descriptions for the system bus configuration, with edge connectors direct

    微處理器系統總線. 8位和16位數據多路總線.第2部分:具有邊緣連接器
  11. Stbus. synchronous split transfer type system bus - logical layer

    同步分離傳遞型系統總線
  12. 821 bus - microprocessor system bus for 1 to 4 byte data

    821總線1至4位元組數據微處理機系統總線
  13. Guide for protective relay applications to power system buses

    電源系統總線的保護繼電器應用指南
  14. It has no effect on bus to adding or removing a bus node

    系統總線各個節點安裝拆卸方便，不影響其它節點的功能。
  15. Communication with the system bus is accomplished via an input / output interface

    與系統總線的通信是由輸入輸出介面來完成的。
  16. The system bus operates at 400 mhz, providing up to 6. 4gb second of bus bandwidth

    系統總線頻率為400 mhz ，提供高達每秒6 . 4gb的總線帶寬。
  17. The trend in hardware has been towards more than one system bus, each serving a small set of processors

    硬體已經趨向使用多條系統總線，每條系統總線為一小組處理器提供服務。
  18. Computers with hardware numa have more than one system bus, each serving a small set of processors

    具有硬體numa的計算機包含多條系統總線，每條系統總線為一小組處理器提供服務。
  19. The meter ( which is called pccm2002 for short ) is designed on the basis of mcs - 51 single - chip microcomputer technique. the hardware is composed of single - chip microcomputer module and electrochemical module. the single - chip microcomputer module can be divided into five parts, cpu circuit, a / d and d / a circuit, peripheral memory circuit, i / o interface circuit, distributing address circuit ; the electrochemical module is made up of potentiostatic circuit, galvanostatic circuit, potentiostatic - galvanostatic ( p - g ) conversion circuit, signal measuring circuit. the software of the meter is edited by c51 language, it is well - structured and module. all program modules have been linked into an executable files after compiled separately, then copy to eprom

    恆電位控制下的恆電量智能化腐蝕監測儀採用基於mcs - 51單片機技術的智能化設計，儀器硬體由單片機系統模塊和電化學介面模塊組成，單片機系統模塊包括cpu電路，片外存貯器擴展電路，模數和數模（ a d和d a ）電路，輸入輸出（ i o ）介面電路，地址分配電路，各電路模塊通過系統總線交換信息；電化學介面模塊主要由恆電位電路，恆電流電路，恆電位-恆電流（ p - g ）轉換電路，信號放大與採集電路組成。
  20. The clb bus is a kind of on - chip system bus which is usually used to connect ips with high speed and high data width. the peripheral bus that conform the pvci standard usually used to connect ips with low speed and low data width

    Clb總線是一種片上系統總線，一般用來連接高速度、高數據寬度的ip 。而符合pvci標準的外設總線上連接的往往是低速度、低數據寬度的ip 。
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