糾錯編碼器 的英文怎麼說

中文拼音 [jiūcuòbiānmǎqì]
糾錯編碼器 英文
error correcting encoder
  • 糾 : Ⅰ動詞1. （纏繞） entangle 2. （集合） gather together 3. （糾正） correct; rectify Ⅱ名詞（姓氏） a surname
  • 錯 : Ⅰ形容詞1 （錯誤; 不正確） wrong; mistaken; erroneous 2 （用於否定: 壞; 差） bad; poor 3 （交叉; ...
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 編碼器 : （將一項信息變換成一系列數碼信號的電路） coder; encoder; encipheror編碼器方框圖 encoder block diagram
  • 編碼 : encoded; code; coded; encrypt; codogram; coding編碼表 encode table; 編碼程序 builder; 編碼尺 code...
  1. Above all, [ 12 : 8 ] harming error correction theory is mentioned in this paper. the edac circuit designed by vhdl can works normally at different frequency of the cpu clock such as 66mhz 50mhz 40mhz 33mhz. the edac function of the circuit can also be disabled by software tool. meanwhile, some basic devices such as and logic, or logic, not logic and some small scale integrated circuits are also integrated in the fpga

    本論文闡述了12 ， 8漢明碼糾錯設計過程，採用vhdl語言實現糾錯編碼器（ edac ） ，本設計能夠適應cpu時鐘信號clk2的不同頻率，如66mhz 、 50mhz 、 40mhz 、 33mhz ，並且能夠通過軟體的控制使fpga的糾錯編碼功能關閉。
  2. Secondly, the thesis designs a kind of scheme of simulcast base station and center base station. and the requisite requirement and chip are introduced here, and the most important controller is atmega128, the avr microcontrollers of atmel corporation. the other roles are played by voice processing circuit, simulcast broadcasting station, data transmission broadcasting station, link transmitter - receiver and gps module etc. and some theory is introduced here, which includes a / d conversion and correct code

    然後，給出了一種同播基站和中心基站子系統的設計方案並簡要說明了所使用的各種設備和晶元，其中最主要的基站控制器由atmel公司的avr單片機atmega128來完成，其它的還包括語音處理電路、同播電臺、數傳電臺、鏈路機、 gps模塊等，並介紹了相關的理論知識，包括a / d轉換，糾錯編碼等。
  3. It also discusses the code and decode theory for rs error - correcting codes, then summarizing the design and debug experience for the rs ( 31, 15 ) coder and decoder through fpga

    文章中還討論了rs糾錯碼的編譯碼原理和演算法，總結了基於fpga實現一個rs （ 31 ， 15 ）編碼和譯碼器的設計經驗和調試經驗。
  4. Our object is an intermediate frequency modem of a software defined radio transmitter - receiver of multi - service, multi - modulationmode and multi - processdatarate. first, related software defined radio theory is introduced ; later, channels of transmitter - receiver are designed with consideration of data format, modulation, fec, interwaving. and scrambling ; emphasis is placed on theory and implementation of an audio compression algorithm cvsd ( continuous variable slope delta modulation ) and a fec technique convolutional coding - decoding

    本文首先介紹了相關的軟體無線電理論；然後完成了包括數據格式，調制方式，糾錯碼方式，交織器和擾碼器等部分的中頻數據機通道設計；接著著重介紹了系統中使用的音頻壓縮演算法cvsd （連續可變斜率增量調制）的原理和實現，以及作為前向糾錯碼的卷積碼編碼理論和編解碼的高效實現。
  5. We put the emphases on the soft output viterbi algorithm ( sova ), which is one of turbo code ’ s decoding algorithms, and presents the derivation and computation step of the sova decoding algorithm. after presenting sova and map decoding algorithms and analyzing four kinds of decoding algorithms, the paper makes a comparison among the different decoding algorithms by emulation analysis, and analyzes the time complexity of various algorithms, and then contrasts them. in the last part of this paper, according to the criterion recommended by the consultative committee for space data systems ( ccsds ), including code rate,

    根據空間數據系統顧問委員會（ ccsds ）為turbo碼應用於深空通信系統推薦的標準，包括碼率、碼塊大小、分量碼類型、約束長度、碼生成多項式，以及交織器的選擇等參數的建議以及sova譯碼演算法的理論基礎，設計了sova演算法的實現結構，通過模擬驗證了本文所採用的turbo碼的性能，從而證明turbo碼確實是一種很好的通道糾錯編碼方式，它適用於要求功耗低或信噪比低的深空通信系統中。
  6. Chapter 5 gives the design illumination of the rs coder and decoder based on fpga. then it gives the integrated results for realization design of the rs ( 31, 15 ) error - correcting code. after that, it gives the functional and layout simulation results for the limited field multiplier, divider, rs coder and rs de - coder

    第五章給出了基於fpga實現的rs編碼器和譯碼器設計說明， rs （ 31 ， 15 ）糾錯碼設計實現的綜合結果，有限域乘法器、除法器、 rs編碼器、 rs譯碼器的功能模擬和布局布線后模擬結果，最後總結主要的調試經驗。
  7. Shows how to correct compiler errors in the code editor through the smart compile auto correction feature

    演示如何使用「智能編譯自動糾正」功能在「代碼編輯器」中糾正編譯錯誤。
  8. In the fec part, rs ( reed - solomon ) code and interleave are chosen as the basic elements of the error correction system at first ; then the coding parameter and data structure are determined based on the results of matlab simulation ; at last, hdl modules are implemented in fpga using verilog hdl, test results and simulation diagrams are presented as well. in the designing process, the proper division of the modules and the cooperation between modules need a lot of consideration, and the top - down method is adopted to solve these questions

    在前向糾錯的設計部分，文章首先根據系統的誤比特率要求選擇了rs （ reed - solomon ）碼和交織器作為前向糾錯部分的基本構架，再根據matlab的模擬結果得到了具體的編解碼參數和碼字結構，最後在fpga中用硬體描述語言veriloghdl實現了各個編解碼模塊，並給出了測試數據、實現結果及時序模擬波形圖。
  9. The compiler derives its name from the way it works, looking at the entire piece of source code and collecting and reorganizing the instructions

    編譯器得名于其工作方式，即將全部程序代碼進行檢查、糾錯和重新組織指令。
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