結構寄存器 的英文怎麼說

中文拼音 [jiēgòujìcúnqì]
結構寄存器 英文
topology register
  • 結 : 結動詞（長出果實或種子） bear （fruit）; form （seed）
  • 構 : Ⅰ動詞1 （構造; 組合） construct; form; compose 2 （結成） fabricate; make up 3 （建造; 架屋） bui...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 結構 : 1 （各組成部分的搭配形式） structure; composition; construction; formation; constitution; fabric;...
  1. Applying two perpendicular polarized light states and a no - light state to express information, this new theoretical system covers : a ) whole architecture constructed from light processing, light transmission, electric control and photoelectric input and output ; b ) various computing units mainly consist of liquid crystal element and polarimeter ; c ) light bus mainly consists of interlinkage optic valves ; d ) ternary memory formed from semiconductor memory ; e ) register formed from optic fiber ring ; and i ) huge - numeral management based on the new concept of calculating path and calculating channel

    這個理論包括：光處理、光傳送、電控制、綜合輸入輸出的總體結構；以液晶元件和偏振器為主的各類運算器結構；以互連光閥為主的光空間總線；以半導體存儲器為主的三值數據存儲器結構；以光纖環為主的寄存器結構；以算位、算道新概念為基礎的巨位數管理方案等。
  2. As one of the design for testability technology, boundary scan test ( bst ) fixes boundary scan cells between the device pins and core logics. thus, the bsc acts as the virtual test probe that carries out the test stimulus and captures the test response

    作為一種結構插入的可測性技術，邊界掃描測試（ bst ）技術將邊界掃描寄存器單元安插在集成電路內部的每個引腳上，其作用相當于設置了施加激勵和觀測響應的內建虛擬探頭。
  3. Risc processors generally feature fixed - length instructions, a load - store memory architecture, and a large number of general - purpose registers and / or register windows

    Risc處理器一般的特徵是固定長度的指令集，一個負載儲備存儲結構，和大量通用寄存器，及寄存器窗口。
  4. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  5. On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology

    本文在分析sparc指令系統的基礎上，研究了流水技術及其相關問題的解決方法，並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、數據相關和轉移相關的問題。
  6. System calls. when an emulator ordinarily encounters a powerpc system call instruction, it emulates the exception by storing the instruction address into the srr0 register, setting some architecture - defined bits in srr1, and transferring control to physical address 0xc00. some powerpc variants allow more control over this behavior, but this is the traditional powerpc model

    當模擬器正常地碰到一個powerpc系統調用指令時，它便將指令地址存入到srr0寄存器，設置srr1中某些體系結構定義的位，並將控制權轉交給物理地址0xc00 ，從而模擬這個異常（有些powerpc的變種允許對這種行為有更多的控制，但是這里的這種是傳統的powerpc模型） 。
  7. With these data structures, code modules, and system registers initialized, the processor can be switched to protected mode by loading control register cr0 with a value that sets the pe flag ( bit 0 )

    當設置好這些數據結構，代碼段以及系統寄存器之後，可以通過設置控制寄存器cr0的pe位（第0位）為1來進入保護模式。
  8. In this paper, we discuss a kind of filter generator whose filter functions have less input bits than the degree of the linear feedback shift register ( lfsr ). by analyzing the structure of the filter generator and its equivalent system, we give out a conditional search algorithm ( csa ) to attack this kind of filter generators

    針對濾波函數f （ x ）的輸入比特數m少於線性反饋移位寄存器級數n的濾波生成器，本文通過分析其等價的組合生成器的結構，以及不同節拍上驅動序列的各個符號之間的制約關系，給出了廣義解序列的概念，並提出了類似遍歷二叉樹的條件搜索演算法csa ，用於攻擊該類特殊的濾波序列。
  9. There are no push or pop instructions and no dedicated stack pointer register defined by the architecture

    體系結構沒有定義壓入或者彈出指令，也沒有定義專門的棧指針寄存器。
  10. Traditional methods such as emulation can do little about it, it has to introduce some new arts. on the path of modern computer and cpu designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus ram, hard disk or floppy disk or flash disk, make up of the modern multi - hiberarchy storage architecture

    現代計算機和cpu設計中， cpu片內的寄存器、一級高速緩存（ level1cache ）和二級高速緩存（ level2cache ） ，主板上的三級高速緩沖，再加上主存，外存（硬盤、軟盤、電子盤等） ，構成了現代計算機的多級存儲體系結構。
  11. These results are then committed to a separate architectural register file during in - order retirement

    這些結果然後在有序退回時，存放在一個獨立的結構寄存器文件中。
  12. Known well vxibus criterion, the structure of configure register and vxi address mapped theory. known well the structure and work theory of high speed synchro data acquisition device

    熟悉vxi寄存器基器件的配置寄存器結構， vxi地址空間映射原理；熟悉高速同步採集卡的總體結構和工作原理。
  13. This text introduced the work patterns and register structure of 80386 processors in detail at first, latterly expounded especially the hardware interrupt handling of windows 98 with the course to the kernel of windows 98 ; then recommended the framework of realization of highly demanding hardware board interrupt handling by revising idt to intercept interrupt handling at hardware layer, subsequently introduced the application and development of vxd technology to achieve interrupt handling overall all situations under the windows 98 platform ; finally introduced the b / s pattern network application development part of this topic, specifically introduced the jsp technology system, elaborated the communication between network application part and the hardware interrupt handling routine combined with the jni technology, and provided partial important program and corresponding commentary

    本文首先詳細介紹了80386處理器的工作模式和寄存器結構，接著對windows98的內核進行了相關分析，重點介紹了windows98的硬體中斷處理過程;隨后介紹了通過修改中斷向量表以實現在硬體層截獲中斷來實現高實時性處理的框架，又介紹了windows98下虛擬設備驅動vxd技術的應用與開發，以及中斷全局處理的實現;最後介紹本課題的b / s模式網路應用開發部分，具體介紹了jsp技術體系，並結合jni技術闡述了網路應用與硬體中斷處理程序的通信，並給出部分關鍵程序及其注釋。
  14. In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl

    在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖，包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹，闡明了使用hdl語言設計超大規模集成電路的一般特點。
  15. A raw ( read after write ) dependency loop model is developed in this paper to analyze the raw hazards of register operands in complex pipeline. based on this model, a " dynamic " data forwarding policy is suggested to reduce the pipeline stalls caused by data raw hazards. theoretical analysis and practical experiments both show that the average cpi increment caused by data raw hazards can be reduced effectively by the dynamic data forwarding strategy

    對于單發射結構的處理器，降低cpi值的根本途徑在於通過各種軟硬體技術減少流水線的停頓，本文構造了一個raw相關環路模型用於分析流水線中寄存器操作數的raw競爭現象，並提出了一種「動態」數據旁路優化策略，可以最大程度地減少復雜流水線中因數據的raw競爭而導致的互鎖停頓，理論分析和實測結果充分表明「動態」數據旁路機構可以有效地降低流水線因raw互鎖導致的平均cpi增量。
  16. In the data path, many modules were designed and implemented, such as alu. data bus unit, w ( work register ) and registers file. the designs of peripheral functional modules were finished, including usart, spi and io

    在詳細分析riscmcu的體系結構特點的前提下，進行了系統劃分，並詳細設計了該riscmcu的數據通路，包括設計該數據通路上的alu單元、內部數據總線、工作寄存器w以及寄存器文件等功能模塊。
  17. A research is done for studying the reusable design principles of bus function model ( bfm ) and bus monitor for reusability. the functional verification framework is proposed in this dissertation can be apply in soc system level, rtl level and gate level verification. we accumulated experiences to soc functional verification

    討論了功能驗證平臺中總線功能模型（ busfunctionmodel ， bfm ）和總線監視器（ busmonitor ）的設計方法，給出了可重用設計的規則；本論文建立的soc功能驗證系統結構，可以應用於較大規模的soc的系統級、寄存器傳輸級和門級的驗證中，通過本課題研究，為國內soc功能驗證積累經驗，為國家超大集成電路的發展奠定一個堅實的基礎。
  18. A typical calculator chip from rcl semiconductor inc, c9821, is referenced and developed. the chip of the calculator consists of several function units such as rc oscillator, power management module, microprogrammed control unit ( mcu ), register group, lcd driver and keyboard interface

    在硬體方面，在完成計算器的功能模塊劃分的基礎上，對包括rc振蕩器、電源模塊、 lcd顯示驅動模塊、鍵盤介面、寄存器組、微程序控制器在內的各個功能模塊的系統結構和電路原理進行了分析，掌握了它們的設計方法。
  19. In the dissertation, we discuss the issues on loop unrolling, register allocation, and cost model, etc. some of the achievements are applied to the implementation of an open source compiler

    本文結合epic體系結構特性，對軟體流水技術中的循環展開、寄存器分配、開銷模型和決策框架等領域進行了研究，並將其中一些成果應於一個開放源碼的編譯器，取得了比較好的效果。
  20. At first, the paper introduces the principle of compacflash card in brief, including internal block diagram, configuration registers, task file registers, addressing mode, data reading and writing, working mode and so on

    論文首先簡要介紹了cf卡的相關內容，包括cf卡的內部結構、寄存器組、尋址方式、數據讀寫、工作模式。
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