綜合邏輯電路 的英文怎麼說

中文拼音 [zōnggěluódiànlù]
綜合邏輯電路 英文
pooling logic circuit
  • 綜 : 綜名詞[紡織] （織布機上使 經線交錯著上下分開以便梭子通過的裝置; 綜片） heddle; heald
  • 合 : 合量詞（容量單位） ge, a unit of dry measure for grain （=1 decilitre）
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 綜合 : 1 （歸在一起; 聯合成一個統一的整體） synthesize 2 （不同種類、不同性質的事物組合在一起） syntheti...
  • 邏輯 : logic
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  2. With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit

    在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。
  3. Thirdly, the paper researchs the application of single electron transistor and the synthesis theory of cicuit based on quantum dot cellular automata by synthesis example of quantum cellular neural network based on build schr ? dinger equation of coupling quantum dot. at last, the paper researchs digital integrated circuit design based on quantum dot cellular automata and design a 8 - bit quantum dot cellular adder by qcadsign based on a method of majority logic reducetion for quantum cellular automata, it prove this designer of 8 - bit quantum dot cellular adder is correctly

    Dinger ）方程為基礎的量子點細胞自動機電路綜合理論，本文以量子細胞神經網路為綜合實例，建立耦合量子點的薛定鄂（ schr ? dinger ）方程組，通過化簡得到類似細胞神經網路的非線性電路方程。最後研究了基於量子點細胞自動機數字集成電路設計，通過建立邏輯方程，簡化邏輯方程，並設計基於精簡qca擇多邏輯門8位加法器，並用qcadesign進行了模擬，實驗證明設計正確性。
  4. Mostly, this design employs mentor corporation software " fpga advantage " as exploitation tool to perform design input 、 simulation and logic thesis with every level and every model to finish the fore design ； then, choices the xilinx corporation product xcv1000 of the vertex series and employ its tool “ allicance series ” to implement layout and timing simulation

    設計主要採用menter公司的功能強大的fpgaadvantage作為開發工具，進行了各個層次、各個模塊的設計輸入、模擬以及邏輯綜合，完成了電路的前端設計；然後選用xinlinx公司的fpga的vertex系列的xcv1000 ，用xinlinx公司的allianceseries工具，進行布局布線，然後再進行時序模擬，生成配置文件。
  5. The digital one includes spec, verilog coding, simulation, synthesis, floorplan, routeing, static timing analyze and drc / lvs check

    數字電路設計流程則包括：制定spec ， verilog代碼編寫，模擬，邏輯綜合，布局，布線，靜態時序綜合和drc lvs檢查。
  6. At the logic synthesis stage, we make some research on the principles of logic synthesis at first, then by utilizing tsmc0. 25um process, choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2. 25v, and introducing the wireload library for effectively simulating delay and power consumption of wire connection, and taking the same clocks as in simulation, the critical path is 15. 3ns and the chip area is 0. 395mm2

    在進行邏輯綜合時首先對邏輯綜合的原理作了一定的了解，然後利用tsmc的0 . 25 m的工藝庫，工作電壓為2 . 25v ，工作溫度最高可達到125攝氏度的最壞情況下，進行邏輯綜合時引入了wireload庫以便有效的模擬連線所引起的延遲及功耗，採用與模擬時相同的時鐘，關鍵路徑為15 . 3ns ，晶元面積為0 . 395mm ~ 2 。
  7. By the top - down way, the design was divided into several modules according to their functions, which were characterized respectively. meanwhile, behavior description, rtl function simulation and logic synthesis were carried out

    在充分了解驅動電路系統的基礎上，採用「自上向下」的設計方法將其劃分為幾個功能模塊，並對它們分別進行了行為描述、 rtl功能模擬、邏輯綜合。
  8. Its driver control logic was realized by means of digital integrated circuit in which the pld chips utilized as the carrier. the vhdl, which is the ieee standard design language of integrated circuit, is used as the behavior description language. the compilation, synthesis, simulation and programming are fulfilled in the maxplusii

    設計的重點是驅動板，其驅動控制邏輯以pld晶元為載體通過數字集成電路方式實現，控制邏輯的功能設計是用ieee標準的集成電路設計語言vhdl作為行為描述語言，在maxplus武漢科技大學碩士學位論文環境中進行編譯、綜合、模擬和晶元編程。
  9. That is to say that ipsec is not suit for the guizhou electric power data network. to this point, after synthesizing the feature of the security, the expansibility and the flexibility, this thesis conclude that mpls vpn is a reasonable way out to connect all parts of businesses and operations in the guizhou electric power system. by this means, different applications run within different vpns, separately in logic, safely and extended well and if necessary, every department can get easy access to the bone net only through a physical interface and interact each other

    在綜合對多協議標記交換虛擬專用網（ mplsvpn ）安全特性的描述，以及mplsvpn固有的高擴展性和靈活性的特點后，為保證各專業系統在骨幹網傳輸的安全性，論文認為完全可以使用mplsvpn的架構，把貴州電力系統的每個業務和相應的vpn對應起來，建議可通過電力數據通信骨幹網mplsvpn方式，不同的應用在各自不同的vpn上，邏輯上相互獨立，安全可靠，並且擴展性好，每家單位只需要一個物理介面接入骨幹網路，即使在同一個局域網上也可將vpn區分出來。
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