編譯碼器 的英文怎麼說

中文拼音 [biānyìmǎqì]
編譯碼器 英文
cldec
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 編譯 : [計算機] compile; translate and edit編譯程序 compiler; compile programme; compiling routine; 編譯...
  1. Chapter 3 discusses the modules used in the fh - mpsk and fh - / 4dqpsk systems. these modules include : duc / ddc ( digital up converter / digital down converter ), nyquist flitter, burst start detection, interpolation module, pll ( phase locked loop ), pll error extraction, initial phase correction and the coding and decoding for tcm

    第三章主要討論了跳頻模式下fh - mpsk和fh - 4dqpsk系統中各個模塊的設計，這些模塊包括：上下變頻器、奈奎斯特濾波器、信號到達檢測、插值模塊、通用環路、各環路誤差提取方法、初始相位校正和tcm編譯碼。
  2. Turbo codes represent the new code structures, which consist of pccc ( parallel serially convolutional code ) and sccc ( serially concatenated convolutional code ). in this paper, the background of turbo codes are firstly introduced, which includes the base principle of error correction code 、 block code and convolutional code ; the principle of turbo code and the iterative decoding is secondly expanded ; the key decoding algorithm : a revised map algorithm and iterative decoding theory are detailed ; then, a new turbo code structure : hccc ( hybrid concatenated convolutional code ) is presented, and the capacity of this code method is analyzed, the average capacity upper bound is derived ; at last, this code is simulated on awgn ( additive white gaussian noise ) channel and rayleigh fading channel

    本文首先介紹了turbo碼的背景知識，包括差錯控制的基本原理、分組碼和卷積碼；然後闡述了turbo碼的基本原理，包括turbo編譯碼器結構及迭代譯碼原理；較為詳細地描述了關鍵的譯碼演算法： ?種改進的最大后驗概率（ map ）譯碼演算法及迭代譯碼演算法；提出了一種新的turbo碼結構：混合turbo碼（混合級聯卷積碼） ；並用編碼性能聯合界分析方法對混合turbo碼進行了性能分析，得出了其平均性能上界；並在高斯白噪聲通道和瑞利衰落通道上分別作了一些應用研究及計算機模擬實驗。
  3. The encoder and decoder used in atm switcher are designed using specific error correcting 1c

    設計了atm交換機中編譯碼器模塊。
  4. 5. according to the euclidean algorithm rs encoder and decoder are implemented in fpga

    根據euclid迭代譯碼演算法，用fpga設計實現了rs碼編譯碼器。
  5. In this paper, the common used encoding algorithms and basic finite - field opera - tions algorithms are introduced, and the decoding algorithms such as inverse - free ber - lekamp - massey ( ibm ) algorithm, reformulated inverse - free berlekamp - massey ( ribm ) algorithm and modified euclidean algorithm are analyzed in great detail. based on the ribm algorithm, a modified structure and a pipelined decoder scheme are presented. a tradeoff has been made between the hardware complexities and decoding latency, thus this scheme gains significant improvement in hardware complexity and maximum fre - quency

    本文簡要介紹了有限域基本運算的演算法和常用的rs編碼演算法，詳細分析了改進后的euclid演算法和改進后的bm演算法，針對改進后的bm演算法提出了一種流水線結構的譯碼器實現方案並改進了該演算法的實現結構，在譯碼器復雜度和譯碼延時上作了折衷，降低了譯碼器的復雜度並提高了譯碼器的最高工作頻率。
  6. It also discusses the code and decode theory for rs error - correcting codes, then summarizing the design and debug experience for the rs ( 31, 15 ) coder and decoder through fpga

    文章中還討論了rs糾錯碼的編譯碼原理和演算法，總結了基於fpga實現一個rs （ 31 ， 15 ）編碼和譯碼器的設計經驗和調試經驗。
  7. The decoder is compiled and simulated in ep1c12q240c by quartusii - 5. 0. the different error style is added to the sequence received in emulated channel. correspondingly, the correct decoding results are attained at the output terminal

    在quartusii - 5 . 0模擬環境下以cyclone系列的ep1c12q240c為目標晶元對譯碼器進行了編譯和模擬，在接收序列中加入不同的錯誤類型，相應的在譯碼器輸出端得出了譯碼后的正確譯碼結果，驗證了設計方案的正確性。
  8. The paper studies the theory and coding methods of the low bit rate video recommendation h. 263 + detailedly, realizes real - time software codec based on h. 263 + under linux os, furthermore, finishes some negotiable coding options which can observably improve the coding efficiency, such as advanced prediction mode, advanced intra coding mode, deblocking filter mode and modified quantization mode

    263 +的原理和編碼方法做了深入的研究，軟體實現了基於h 263 +標準的視頻編譯碼器在linux操作系統下的實時編解碼，並實現了能顯著提高編碼效率的幾種可選編碼模式，主要包括先進預測模式、先進幀內編碼模式、塊邊界濾波模式和改進量化模式等。
  9. Evaluation package for mpeg - 2 coder and decoder show its appearance on the market

    2編譯碼器評價組件亮相
  10. Enhanced variable rate codec speech service option 3 for wideband spread spectrum digital systems

    寬帶頻譜擴展數字系統用增強的可變率編譯碼器語音服務選擇3
  11. Finally, a total design scheme that realizes the stbc is shown and the software which supports the platform is also given

    之後，給出了空時分組碼編譯碼器的硬體總體設計方案，闡述了軟體的具體實現過程。
  12. Therefore, the research targets of this dissertation are to realize the coding and the decoding of stbc after studying its theory

    本文在研究了空時分組碼的理論基礎上，對其編譯碼器進行了硬體模擬實現。
  13. Evrc 3 software distribution for tia - 127 - a - enhanced variable rate codec speech service option 3 for wideband spread spectrum digital systems

    Tia - 127 - a的軟體配置.寬帶頻譜擴展數字系統用增強的可變率編譯碼器
  14. Improve on algorithms can enhance encoding / decoding performance. with pipeline and systolic array architectures adopted in the hardware implements, encoder / decoder based on fpga can work better

    對編譯碼演算法的改進有助於提高rs編譯碼器的性能，而利用fpga來實現rs編譯碼器，並採用流水線、心縮式陣列等優化結構，更能提高編譯碼器的性能。
  15. This paper discussed the theory of encoding and decoding of turbo codes, researched some key techniques in encoder and decoder, analyzed the question of selection of the component codes and generation polynomial in encoder

    本文討論了turbo碼的編譯碼原理，研究在其編譯碼器中的關鍵技術，重點探討了在編碼器中成員碼以及生成多項式的選擇問題。
  16. Although the structure of stbc decoding is very simple, it can achieve the same diversity gain as the method of mrc, and its use of the spectrum is very high. because of these advantages, sttb is referred into the 3gpp1

    由於空時分組碼編譯碼器的結構相當簡單，卻能獲得與最大比合併相同的分集增益，並且它的頻譜利用率高，已經被引用到3gpp1中。
  17. Firstly, this paper discusses several algebraic algorithms for encoding and decoding reed - solomon codes from the view of engineering. then their applications in atm and dvb systems are investigated particularly. finally, fpga implementation of reed - solomon codes is discussed

    本文主要是從工程應用的角度，討論了rs碼的幾種編譯碼演算法，並且著重論述了rs碼的兩個應用和如何用fpga設計編譯碼器。
  18. The paper expounds on the theory, concept and application of reed - solomon code by the brief introduction of error controlling system and channel coding, and finally finishes the design of rs code coder and decoder under the guidance of dvb - c standards by consulting the related references

    本論文通過對差錯控制系統及通道編碼的簡單介紹，進而闡述了reed ? solomon碼的原理、概念和應用，參考有關文獻，完成了在dvb - c標準下對rs碼編譯碼器的演算法的程序編制和硬體的結構設計。
  19. After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance

    經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。
  20. In the third chapter, the principles of randomizer and de - randomizer are illuminated, and the hardware realization is also given. the fourth chapter is focused on the design of ip ( intellectual property ) and the analysis of the principle of rs encoding and decoding. based on the theory of design reuse in soc ( system on chip ), this chapter is devoted to the design and implementation of rs decoder ip which can be implied in three hdtv channel decoder standard

    第四章首先介紹了ip的基本知識和設計流程，接著對rs碼的編碼和譯碼進行詳細的理論分析研究，提出rs編譯碼器實現方法，然後根據soc可復用設計設計思想，設計了一個應用於hdtv通道解碼的rs譯碼ip核，最後給出dvb - crs譯碼器的asic設計，並給出了其規模和性能。
分享友人
分享到 Line

分享到臉書