緩沖器插入 的英文怎麼說

中文拼音 [huǎnchōngqìchārù]
緩沖器插入 英文
buffer insertion
  • 緩 : Ⅰ形容詞1 （遲; 慢） slow; unhurried 2 （緩和; 不緊張） not tense; relaxed Ⅱ動詞1 （延緩; 推遲） d...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 插 : 動詞1. （把細長或薄的東西放進、擠入、刺進或穿入; 插上; 插進） stick in; insert 2. （中間加進去; 加進中間去） interpose; insert
  • 入 : Ⅰ動詞1 （進來或進去） enter 2 （參加） join; be admitted into; become a member of 3 （合乎） conf...
  • 插入 : insert; infix; run in; break in; patch; insertion; plug in; intercalate; intercalation; intromiss...
  1. An algorithm of path - based timing optimization by buffer insertion is presented. the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation. and heuristic method of buffer insertion is presented to reduce delay. the algorithm is tested by industral circuit case. experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied

    提出了一種基於路徑的緩沖器插入時延優化演算法，演算法採用高階模型估計連線時延，用基於查表的非線性時延模型估計門延遲.在基於路徑的時延分析基礎上，提出了緩沖器插入的時延優化啟發式演算法.工業測試實例實驗表明，該演算法能夠有效地優化電路時延，滿足時延約束
  2. Applies the vertex processing defined by the vertex shader to the set of input data streams, generating a single stream of interleaved vertex data to the destination vertex buffer

    將頂點著色器定義的頂點處理過程應用到輸入數據流組，從而生成從插入的頂點數據到目標頂點緩沖區的單個流。
  3. After being read in from dasd, the data and index pages go into these slots and remain there until the db2 buffer manager determines that those slots should be used for some other data

    數據和索引頁被從dasd中讀出之後，便進入這些插槽，並留在其中，直到db2緩沖區管理器確定那些插槽要用於其他數據。
  4. Path - based timing optimization by buffer insertion with accurate delay model

    採用精確時延模型基於路徑的緩沖器插入時延優化
  5. Abstract : an algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented. given a two - terminal net, the algorithm can minimize the total number of buffers inserted to meet the delay constraint. a high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look - up table is for buffer delay estimation. the experimental results show that the algorithm can efficiently achieve the trade - offs between number of buffers and delay, and avoid needless power and area cost. the running time is satisfactory

    文摘:提出了在精確時延模型下，滿足時延約束的緩沖器數目最小化的演算法.給出一個兩端線網，該演算法可以求出滿足時延約束的最小緩沖器數目.運用高階時延模型計算互連線的時延，運用基於查找表的非線性時延模型計算緩沖器的時延.實驗結果證明此演算法有效地優化了緩沖器插入數目和線網的時延，在二者之間取得了較好的折中.演算法的運行時間也是令人滿意的
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