縮寫和代碼 的英文怎麼說

中文拼音 [suōxiěhédàimǎ]
縮寫和代碼 英文
abc abbreviations and codes
  • 縮 : 縮構詞成分。
  • 寫 : 寫構詞成分。
  • 和 : 和動詞（在粉狀物中加液體攪拌或揉弄使有黏性） mix （powder） with water, etc. : 和點兒灰泥 prepare some plaster
  • 代 : Ⅰ動詞1 （代替） take the place of; be in place of 2 （代理） act on behalf of; acting Ⅱ名詞1 （歷...
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 縮寫 : 1 [語言學] abbreviation: mathematics 有時縮寫成 math 。 mathematics is sometimes abbreviated to m...
  1. Epc is the abbreviation of electronic product code. it is the exclusive and discriminated code which auto - id center distributes to every product. it uses a series of number as the representative of manufacturer, product type and product serial number which exclusively discriminate a product

    Epc （ electronicproductcode ）是產品電子碼的縮寫，是auto - id研究中心為每一件產品分配的一個唯一的、可識別的標識碼，它用一串數字代表產品製造商，產品類別和唯一標識每一個特定產品的產品序列號。
  2. Using draw2d to write your own java language code to plot charts and graphs can help you concentrate on scaling and plotting code, leaving the rendering painting related jobs to draw2d and swt

    可以使用draw2d編寫自己的用來繪制圖形的java代碼，這有助於您將精力集中於縮放代碼和繪制代碼上，把其他與繪制相關的工作留給draw2d和swt 。
  3. The dissertation compiles and develops error resilience function module, which is based on mpeg - 4 ( iso 14496 ) video part that is compatible with first generation and is ground on visual object. it is founded on familiarity with syntax and semantic of mpeg - 4 video. and the decoder refers to no error resilience deocder and decodes mpeg - 4 iso encoder coded video data streams

    本文以國際壓縮標準mpeg - 4 （ iso14496 ）這一兼容第一代壓縮演算法的基於視頻對象的視頻部分iso14496 - 2 ）為平臺，在熟悉mpeg - 4視頻流語法和語義的基礎上，對mpeg - 4iso - encoder視頻編碼器編碼的數據流，參照其沒有錯誤恢復的視頻解碼器，編寫、增加視頻容錯演算法處理模塊。
  4. The thesis then introduces top - to - bottom schemes, which discuss the functional design of hdtv test pattern signal generator according to the tasks and platform of the system, and develops the function of subsystems. the thesis analyses the theory and mathematic model of hdtv test signal, and studies the signal generating scheme called single - fpga and multi - prom, and describes in detail its key modules such as configuration connecting, prom routing, control and switch timing design and so on. the single - fpga and multi - prom scheme increases the number of prom to reduce the degree of fpga demanded, thus

    論文分析了hdtv測試信號的原理及數理模型，提出了一種以單晶元多配置為特色的信號生成方案，並對該方案的配置連接、晶元選路、控制切換時序設計等關鍵模塊進行了詳細敘述，該方案以增加配置晶元數量來降低對主晶元要求，不但降低了產品成本，還使各測試信號的代碼編寫和產生相對獨立，有利於合理使用晶元資源，實現多種復雜的hdtv測試信號，縮短開發周期。
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