行寄存器 的英文怎麼說
中文拼音 [hángjìcúnqì]
行寄存器
英文
line register-
The parallel number is applied to the shift register.
并行數寄存於移位寄存器。The shift register is a device in which information may enter sequentially or in parallel.
移位寄存器是一種能以串列和并行方式輸入信息的裝置。The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data
具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。Because no drive software is needed in using chip 21154, this paper don ’ t refer to the drive design. after configuring the register in initialization rightly, the work about design of add - in card are all done
因為橋晶元不需要驅動軟體，因此不需要進行驅動程序的設計，只需要在初始化的時候對配置寄存器進行正確的配置即可，這些工作在最後一部分完成。Enables advanced features for debugging at the address level the disassembly window, registers window, and address breakpoints
啟用在地址級上進行調試的高級功能（ 「反匯編」窗口、 「寄存器」窗口和地址斷點） 。The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl
該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。System calls. when an emulator ordinarily encounters a powerpc system call instruction, it emulates the exception by storing the instruction address into the srr0 register, setting some architecture - defined bits in srr1, and transferring control to physical address 0xc00. some powerpc variants allow more control over this behavior, but this is the traditional powerpc model
當模擬器正常地碰到一個powerpc系統調用指令時，它便將指令地址存入到srr0寄存器，設置srr1中某些體系結構定義的位，並將控制權轉交給物理地址0xc00 ，從而模擬這個異常（有些powerpc的變種允許對這種行為有更多的控制，但是這里的這種是傳統的powerpc模型） 。Lcd will display wanted data by writing data to specified instruction register and specified data register through control bus and data bus, which makes operation easier
只要通過數據線和控制線對指定的寄存器進行操作即可對想要顯示的數據進行顯示，開發起來很容易。The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation
再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。Other segments can be made available by loading their segment selectors into these registers during program execution
要想使用其它的段，可以在程序運行時把這個段選擇子載入段寄存器中。These instructions change the contents of the cs register ( and sometimes other segment registers ) as an incidental part of their operation
而這類指令在執行時會修改cs （或其它段寄存器）的內容。The information of running programs users can get is just the register, memory and symbol state
所看到的程序執行現狀，也只是目標機方當前程序寄存器、內存、符號信息等基本信息。All instructions are carried out using a register called the accumulator, which we shall denote by a.
全部指令執行時都用了稱作累加器的寄存器（用符號A來表示）。Accumulator and index register can be accessed by the programmer
程序員可以對累加器和變址寄存器進行存取。Secondly, the encoder circuit of quasi - cyclic which can realize low encoding complexity are designed and implemented. three encoder circuit are designed respectively with feed shift - registers and logic gates : sraa - based serial qc - ldpc encoder ; sraa - based parallel qc - ldpc encoder ; two - stage qc - ldpc encoder
採用反饋移位寄存器與邏輯門設計了三個典型的編碼器電路:基於sraa電路的串列準循環ldpc碼編碼器;基於sraa電路的并行準循環ldpc碼編碼器;二階編碼電路。The part of execution in which an operand or instruction is read from main stora ge and written into a control unit or arithmetic unit register
執行過程中的一個階段所需的時間，在此期間，計算機從主存儲器中取出指令或操作數，並將其存入控制器或運算器的寄存器中。These allow you to stop at procedure locations, inspect memory and register values, change variables, observe message traffic, and get a close look at what your code does
這些功能使您可以在某些過程位置停止執行，檢查內存和寄存器值，更改變量，觀察消息通信量，以及仔細查看代碼的行為。For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively
摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。Computer architecture, barcelona, spain, june 27 - july 1, 1998, pp. 282 - 292. 6 buyuktosunoglu a et al. a circuit level implementation of an adaptive issue queue for power - aware microprocessors
2對位於第二級的發射隊列利用寄存器標簽進行多體劃分，更進一步減小發射隊列的大小和比較器的位寬。Due to the development of 1c technology, now a complex system can be integrated in a chip called system on chip ( soc ). the design of soc needs new design methodologys and modeling tools. systemc is an open c + + modeling platform promoted by the open systemc initiative, which consists of a well defined set of c + + classes and a simulation kernel, supporting design abstractions at the register - transfer, behavioral, and system levels. the advantages of systemc include the ability for hardware - software co - design, the ability to exchange ip easily and efficiently, and the ability to reuse test benches across different levels of modeling abstraction
系統級晶元的設計需要新的設計方法和建模工具。 systemc是osci （ opensystemcinitiative ）組織制定和維護的一種開放源碼的c + +建模平臺，它由一個定義良好的c + +類庫及模擬內核組成，支持對系統進行寄存器傳輸級，行為級和系統級的描述。 systemc的優點包括對軟硬體聯合設計的支持，更高效和方便的進行ip交換，以及在不同的抽象模型間復用測試基準的能力。分享友人