表寄存器 的英文怎麼說
中文拼音 [biǎojìcúnqì]
表寄存器
英文
table register-
All instructions are carried out using a register called the accumulator, which we shall denote by a.
全部指令執行時都用了稱作累加器的寄存器（用符號A來表示）。A computer storage position or register, whose contents identify a particular element in a table
一種計算機存儲器單元或寄存器，它的內容標識一個表中的特定元素。Meanwhile, the implementation of such block cipher as rijndael with shifting registers is designed with performance as good as that of he method of table - lookup
將移位寄存器實現高效流密碼的思想用於分組密碼rijndael演算法的實現，獲得與查表法相當的效率。It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function
本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. from the layout simulation result, under the 0. 18um process, the upper limit working frequency for the register file is 900mhz
本文面向一款具有完全自主知識產權的64位高性能通用處理器，對其中具有代表性的128字65位12讀埠和8寫埠的通用寄存器文件進行研究，實現了它的高速讀寫全定製設計，版圖模擬結果表明，在0 . 18um工藝下，設計可以工作的時鐘頻率上限為900mhz 。Assembly - language instructions consist of mnemonics, which are abbreviations for instruction names, and symbols that represent variables, registers, and constants
匯編語言指令由助記符（指令名稱的縮寫）和代表變量、寄存器以及常量的符號所組成。Rat register alias table. during resource allocation the renaming of logical to physical registers is performed here
寄存器別名表。當資源再行分配時，對物理寄存器進行邏輯的重命名。Fields would be made directly to main memory, instead of to registers or the local processor cache, and that actions on volatile variables on behalf of a thread are performed in the order that the thread requested
欄位的讀寫直接在主存而不是寄存器或者本地處理器緩存中進行，並且代表線程對volatile變量進行的這些操作是按線程要求的順序進行的。This text introduced the work patterns and register structure of 80386 processors in detail at first, latterly expounded especially the hardware interrupt handling of windows 98 with the course to the kernel of windows 98 ; then recommended the framework of realization of highly demanding hardware board interrupt handling by revising idt to intercept interrupt handling at hardware layer, subsequently introduced the application and development of vxd technology to achieve interrupt handling overall all situations under the windows 98 platform ; finally introduced the b / s pattern network application development part of this topic, specifically introduced the jsp technology system, elaborated the communication between network application part and the hardware interrupt handling routine combined with the jni technology, and provided partial important program and corresponding commentary
本文首先詳細介紹了80386處理器的工作模式和寄存器結構，接著對windows98的內核進行了相關分析，重點介紹了windows98的硬體中斷處理過程;隨后介紹了通過修改中斷向量表以實現在硬體層截獲中斷來實現高實時性處理的框架，又介紹了windows98下虛擬設備驅動vxd技術的應用與開發，以及中斷全局處理的實現;最後介紹本課題的b / s模式網路應用開發部分，具體介紹了jsp技術體系，並結合jni技術闡述了網路應用與硬體中斷處理程序的通信，並給出部分關鍵程序及其注釋。Compile - time variables are represented in machine registers and directly - accessed memory locations, once the operations have been compiled by psyco into machine code
一旦psyco將操作編譯成機器碼，那麼編譯時變量就會在機器寄存器和可直接訪問的內存位置中表示。A raw ( read after write ) dependency loop model is developed in this paper to analyze the raw hazards of register operands in complex pipeline. based on this model, a " dynamic " data forwarding policy is suggested to reduce the pipeline stalls caused by data raw hazards. theoretical analysis and practical experiments both show that the average cpi increment caused by data raw hazards can be reduced effectively by the dynamic data forwarding strategy
對于單發射結構的處理器，降低cpi值的根本途徑在於通過各種軟硬體技術減少流水線的停頓，本文構造了一個raw相關環路模型用於分析流水線中寄存器操作數的raw競爭現象，並提出了一種「動態」數據旁路優化策略，可以最大程度地減少復雜流水線中因數據的raw競爭而導致的互鎖停頓，理論分析和實測結果充分表明「動態」數據旁路機構可以有效地降低流水線因raw互鎖導致的平均cpi增量。Information technology - international standardized profiles fvt3nn - virtual terminal basic class - register of attribute assignment type definitions - fvt311 - repertoire assignment type for iso iec 10646
信息技術.國際標準化的剖面圖fvt3nn .虛擬終端基本類型.屬性分配類型定義寄存器. fvt311 . iso iec的指令表分配類型Contains values that represent the registers associated with a given processor architecture
包含表示與指定處理器結構關聯的寄存器的值。That represents the value of an argument or local variable stored in two memory registers of a native frame
獲取一個指針，該指針指向表示兩個內存寄存器中存儲的參數或局部變量值的No. 1 information technology. international standardized profiles fvt2nn. virtual terminal basic class. register of control object type definitions. part 10 : fvt231. forms fepco field entry pilot control object no 1. european standard en isp 11185 - 10
信息技術.國際標準輪廓fvt2nn .虛擬終端基本類型.控制目標類型定義寄存器. fvt231 . fepco表Information technology - international standardized profiles fvt2nn - virtual terminal basic class - register of control object type definitions - fvt2112 - printer control object
信息技術.國際標準數據區fvt2nn .虛擬終端基礎分類.控制對象類型定義寄存器. fvt2112 .印表機控制對象All instructions are carried out using a register called the accumulator, which we shall denote by a
全部指令執行時都用了稱作累加器的寄存器（用符號a來表示） 。It also frees one more register, ebp on the intel 386 or later for storing frequently used variables and sub - expressions
它還可以使一個或多個寄存器（ intel 386或更高版本中的ebp ）空閑出來，將其用於存儲頻繁使用的變量和子表達式。For each register we create a queue and the index of queue item means a function of executing time. the item in the queue is either null or an instruction whose operand is kept in this register
該演算法利用寄存器隊列分析指令間的數據相關，能夠分析出指令間的所有寄存器相關，其特點是：數據流驅動；演算法簡單、實現效率高；并行成分的表示直觀。Calculation for the data from simulation shows that power dissipation of det shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart set shift register
對模擬所得數據的計算結果表明，與實現相同功能的單邊沿移位寄存器相比，由於工作頻率減半，雙邊沿移位寄存器的功耗有明顯降低。分享友人