襯底效應 的英文怎麼說

中文拼音 [chèndexiàoyīng]
襯底效應 英文
body effect
  • 襯 : Ⅰ動詞1 （在裏面托上一層） line; place sth underneath 2 （陪襯; 襯托） set off Ⅱ名詞（襯在裏面的附...
  • 底 : 底助詞（用在定語后, 表示定語和中心詞之間是領屬關系, 現在多寫作「的」）
  • 效 : Ⅰ名詞（效果; 功用） effect; efficiency; result Ⅱ動詞1 （仿效） imitate; follow the example of 2 ...
  • 應 : 應動詞1 （回答） answer; respond to; echo 2 （滿足要求） comply with; grant 3 （順應; 適應） suit...
  • 效應 : [物理學] effect; action; influence
  1. Author analyzed the relationship between the length and the impurity concentration of drift region and thickness of buried oxide layer and thickness of soi and the charges of oxide layer and bias voltage of bulk and breakdown voltage and on - resistance by numerical simulation

    採用數值模擬分析方法，深入研究了漂移區長度、漂移區濃度、埋氧層厚度、頂層硅厚度、氧化層電荷以及襯底偏壓對resurf效應、擊穿電壓和導通電阻的影響。
  2. With an analysis of soil liquefaction potential for free field of nanjing metro line 1 under 7 degree earthquake, as well as for excavated field, in line with railway engineering anti - earthquake design specification, dynamic triaxial tests and theoretical analysis using efficient stress method, the author comes to the conclusion that, when metro plate is located at layer s and the layer is thick, liquefied area is at metro bottom plate ; in some local section liquefied area is at metro top plate, or arch sides at the top of metro in most places

    摘要採用鐵路工程抗震設計規范、動三軸試驗及有效應力的理論分析相結合的方法，對南京地鐵南北線（ 1號線）區間隧道開挖后其地基土在7度地震情況下的土層液化情況進行分析得出：當隧道底板坐落在5層且5層較厚時的液化區出現在隧道襯砌底板處；局部地段液化區出現在隧道頂部及拱腰；大部分地段的液化區出現在隧道頂板上方。
  3. Account for the high electrical field induced from the high applied voltage relative to small dimension device, the mechanism of hot - carrier generation is analysed, the si - h bond broken model for hot - carrier injection and interface states generation is deduced and the substrate current model is developed

    基於mosfet偏壓不能按比例縮小所導致的高電場，對mosfet的熱載流子產生機理進行了分析，導出了熱載流子注入所引起的界面態的si - h健斷裂模型，並建立了表徵器件熱載流子效應的襯底電流模型。
  4. We researched fabrication at different asputtering and annealing atmosphere, the different process conduced different electrical properties. we can conclude a higher annealing temperature and higher proportion of o2 during reactive sputtering favors the improvement of electrical performances of hfo2 dielectrics ; 4. the analysis of i - v curves of these devices displays different leakage current mechanism under different area of applied bias - voltage ; as to silc. there are different leakage current mechanism at influence of sil. c ; 5

    研究表明，在優化工藝條件下制備的hfo _ 2介質層中，襯底注入條件下由於其較低的體和界面缺陷密度，漏電流的輸運機制主要以schottky發射為主; silc效應導致hfoz / si界面缺陷態的增加，從而使得襯底注入條件下，柵泄漏電流機制不僅有schottky發射還有f一p發射機制起主要作用; 5 ）初步研究了氮化的hfo : （ hroxny ）柵介質的電學特徵。
  5. Preparation of steel substrates before application of paints and related products - collected information on the effect of levels of water - soluble salt contamination

    塗料和相關產品使用前的鋼襯底處理.水溶鹽污染物等級效應的採集信息
  6. Because linbo _ 3 material have the characteristics such as good electro - optic, short electro - optic time response and high transnissivity, it is suitable substrate material used as manufacturing low loss waveguid device and has broad application prospects

    由於linbo _ 3材料具有良好的電光效應、較短的電光響應時間和高透射率特性，因而適宜製作低損耗導波器件的襯底材料，應用前景廣闊。
  7. The n / n + and p / p + epitaxial structures, which become popular with the development of coms technology, because they can avoid the latch - up and a softerror of ulsi while they combined with the intrinsic gettering ( ig ) technique

    Coms工藝中普遍採用n / n ~ + 、 p / p ~ +的外延結構，這種以重摻雜矽片為襯底的外延結構與內吸雜工藝相結合，是解決集成電路中的閂鎖效應和粒子引起的軟失效的有效途徑。
  8. It also has short protection and voltage overshot protection block. devices and ics based on esoi have the advantages of not only cheaper substrate, good performance of soi technology, but also obtaining a certain breakdown voltage and optimization of self - heating effect

    基於esoi的器件及集成電路不僅襯底材料制備工藝簡單，硅層厚度均勻性好，器件及電路特性具有soi結構的優點，而且還兼顧一定的耐壓，對自加熱效應也得到優化。
  9. The size of the zno nanocrystal grain was so little that the quantum confinement effect should be considered. that makes the band gap wide. atom transfer rate is affected by the substrate temperature, and the average size of the zno nano crystal grain increases with the increasing substrate temperature resulting in the red shift of pl emission position and the narrowness of pl fwhm

    低溫生長的氧化鋅晶粒小，考慮到量子限制效應，禁帶寬較大；襯底溫度影響吸附原子遷移能力，隨著溫度升高，晶粒的尺寸增大，分佈變的均勻，因而發光峰位隨著襯底溫度的升高而紅移，發光的半高寬變小。
  10. Based on the photoelectron and microelectronics, communication and net technology has become the core of high - tech. as the main carriers of information technology, lasers and display devices play significant roles. compare to the inorganic semiconductors, the organic semiconductors have much advantages

    以多種工藝在硅基襯底和玻璃襯底上制備了不同結構的有機薄膜場效應晶體管（ otft ） ，論述了不同制備工藝的優缺點，以及器件結構對性能的影響。
  11. Especially, mesfet devices fabricated on lec si - gaas substrate have been adopted into very large - scale integration ( vlsi ) and monolithic microwave integrated circuit ( mmic ) extensively. therefore, it is necessary to study the influence of defects in substrate material of lec si - gaas on performance of mesfet to meet the need of design and fabrication of gaas ic

    以液封直拉半絕緣gaas為襯底的金屬半導體場效應晶體管（ mesfet ）器件是超大規模集成電路和單片微波集成電路廣泛採用的器件結構，因此研究lec法生長si - gaas （ lecsi - gaas ）襯底材料特性對mesfet器件性能的影響，對gaas集成電路和相關器件的設計及製造是非常必要的。
  12. 2. based on the kinematics, we have analyzed in detail the problems such as substrate diffraction, thin layer effect and instrument effect in applying the kinematics in material analysis and provided corresponding solve

    2 .基於運動學理論，結合外延材料的實際特點，分析了將運動學理論應用於實際材料分析時需要著重考慮的襯底衍射、薄層效應、儀器效應等問題並給出了相應的解決方案。
  13. The degradation and lifetime model is deeply discussed, dynamic and static stress suffered by devices and circuits are compared and analyzed. a modified model for lc is proposed for better fitting the experimental data and the substrate current model parameters eerit and lc, degradation parameter h, m, n are extracted by the static stress experiment results

    詳細分析討論了mosfet的壽命與退化模型，並對電路中器件所受的動態應力與直流靜態電應力進行了分析比較：根據實驗結果改進了有效導電長度l _ c模型；應用直流電應力實驗數據進行了襯底電流模型中載流子速度飽和電子科技大學博士論文臨界電場e ； 、有效導電長度lc以及退化參數h 、 m和n的提取。
  14. 2 ) the p - n heterjunction effects between b - implanted diamond films and n - type si substrate was investigated

    2 ）研究摻b的金剛石膜和n型si襯底之間的半導體p - n結效應研究。
  15. Polycrystalline diamond films were deposited on n - type si substrates. in order to achieve a better distribution of the implanted element, boron ions were implanted by two steps. the i - v curves were studied, the p - n junction effect is very evident

    在n型引襯底上沉積一層連續的金剛石膜，通過二次離子注入的方法使b離子比較均勻的分佈在金剛石膜中，通過測量i - v曲線，可以明顯的看出p - n結效應的存在。
  16. And for analog applications by adding a normally - on nmosfet in series with the n - mosfet in an analog circuit respectively. according to spice3f5 and bert2. 0 simulation results, the substrate current of new structure cmos inverter is suppressed to about 50 % of its original value and good hot - carriers resistant behaviors are obtained without adding any extra delay

    0對倒相器的模擬結果表明：新型cmos數字電路結構結構使襯底電流降低約50 ，器件的熱載流子退化效應明顯改善而不會增加電路延遲；巳該電路結構中肖特叢一級管可在nmosfet漏極亙接製作肖特基金半接觸來方便地實現，工藝簡單又無須增加晶元而積。
  17. It is shown that substrate current is not the good indication of hot carrier effect in sde structures and using a threshold degradation criterion to characterize device degradation is not suitable for sde structures. third, the effect of the sde implant dose on the hot carrier immunity is thoroughly studied

    在此基礎上，指出採用峰值襯底電流評估sde結構器件可靠性的局限性，以及在採用i - v特性測試方法研究sde結構器件的熱載流子效應時，閾值電壓作為退化判據所存在的問題。
  18. The laser induced thermoelectric voltage effect had been found in lcmo and ybco thin films grown on tilted substrates due to heating by laser radiation

    傾斜襯底上生長的lcmo及ybco薄膜具有激光感生電壓效應。
  19. The dominance and properties of the cmos integrated reference were also described, and the research meaning was pointed out. related device theory and process model used in design were described. the temperature related model and the influencing factor of two active devices, subthreshold mosfet and pnp substrate transistor, based on cmos process were analyzed and compared, and pointed out that the pnp substrate transistor was more fit for being the temperature compensating device for bandgap reference

    闡述了設計中相關的器件理論與工藝模型，對cmos工藝下的兩種有源器件，即亞閾值工作狀態下的金屬場效應晶體管（ mosfet ）及襯底pnp雙極型晶體管（ bjt ）的溫度模型及其影響因素進行了分析和比較，指明襯底pnp雙極型晶體管更適合作為基準源的溫度補償元件。
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