視頻解碼晶元 的英文怎麼說

中文拼音 [shìbīnjiěmǎjīngyuán]
視頻解碼晶元 英文
video decoder
  • 視 : Ⅰ動詞1. （看） look at 2. （看待） regard; look upon 3. （考察） inspect; watch Ⅱ名詞（姓氏） a surname
  • 頻 : Ⅰ形容詞（次數多） frequent Ⅱ副詞（屢次） frequently; repeatedly Ⅲ名詞1 [物理學] （物體每秒鐘振動...
  • 解 : 解動詞（解送） send under guard
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 視頻 : [物理學] video frequency （v f ）; vision frequency; visual frequency; video視頻變頻器[變換器] vi...
  • 解碼 : decoding; decipher; decode
  1. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  2. The paper is to design analogue lowpass filtering circuits with high performances. the circuits are used directly as anti - alias filters in an analogue front - end of video decoder ic ( integrated circuit )

    =本文旨在設計高性能的模擬低通濾波電路，用作視頻解碼晶元模擬前端中的抗混疊濾波器。
  3. The function of video frequency gathering board is to reveal the compound television signal from the computer to carry on a / d transforms, rgb separation processing and so on, output 24bits rgb signals and the synchronized signals. these functions were finished by video frequency decoding chip saa7111 made by philip corporation

    視頻採集板的功能是利用philip公司的視頻解碼晶元saa7111 ，對計算機顯卡輸出的復合電視信號進行a / d轉換， rgb分離等處理，輸出24位rgb信號和同步信號。
  4. Introduces operation principle and interface circuit design of video input processor saa7111 and video output processor saa7185. 4

    介紹了可編程視頻輸入編碼晶元saa7111和可編程視頻解碼輸出晶元saa7185工作原理和介面電路設計。
  5. First an analog video signal is decoded by saa7 11 a to form a digital video signal complying with ccir6o1 which then is compressed by an special chip ibms42o, at last, the video es is packed with audio es to form ts by computer

    具體來說，是把模擬視頻源解碼成符合ccir601規范要求的數字視頻源，經專用的mpeg2編碼晶元壓縮形成視頻es流送入計算機，與一路音頻es流打包復用后形成一路ts流。
  6. By systemview, hdl simulation and fpga verification, the results showed that the decoder met commercial ic requirements

    經systemview ， hdl模擬及fpga驗證，結果表明:所設計的數字視頻解碼電路的各項性能達到了晶元商用要求。
  7. The fifth chapter expatiate the resolve method of false code during the video processing. the emphasis is put on the false code resolve method in video post - processing. these methods are adopted in many video processing chips include sti5518

    闡述了對于視頻處理過程中誤碼的解決方法，著重對于視頻后處理過程的誤碼檢測和掩蓋方法進行了說明，這些方法也是現行解碼晶元普遍使用的誤碼解決方案。
  8. Introduces operation principle and interface circuit design of video codec adv611. 3

    介紹了新一代視頻編解碼晶元adv611的工作原理和介面電路設計。
  9. On designing of the encoder, by using the decoding for video chip saa7113 made in philips, analog video signal inputted realizes a / d conversion in analog / power block

    編碼器的設計中，模擬/電源塊主要實現的功能是對輸入的模擬視頻信號進行a / d轉換，解碼晶元採用philips公司saa7113 。
  10. Digital - video encode - decode chip, one of the basic components of digital - video devices, is still relying on import products

    數字視頻解碼晶元是數字電視等視聽設備的核心器件，目前絕大多數仍依賴國外進口。
  11. This paper focuses on principles of the controller in dtv ( digital television ) channel receiving chip and its realization in asic

    本文著重於有線視頻廣播傳輸系統中通道解碼晶元的控制部分的基本原理及其在專用集成電路晶元（ asic ）上的具體實現。
  12. This paper is to discover the clamp circuits for realizing video decoder ic ( integrated circuit ), and focusing on realizing the function of video clamp circuit and project design with cmos process

    本文旨在探索為實現視頻解碼晶元的模擬前端而作的箝位電路設計。重點論述了在cmos工藝下視頻箝位電路的功能實現及設計方案。
  13. The application of hardware decoding circuit is widely, because it not only can be used on computer, but also can be used on consumer equipment like digital - tv and dvd - player. the avs and h. 264 standards and the architecture of digital video decoder chip are investigated in the thesis, and a high - definition multi - mode decoder soc chip is proposed. the chip can support avs level 4. 0 / 6. 0 and h. 264 main profile level 4. 0

    本文在研究了avs和h . 264視頻編碼標準和數字視頻解碼晶元系統結構的基礎上，設計了同時支持avs和h . 264的高清解碼soc晶元，能夠對avslevel4 . 0 / 6 . 0和h . 264mainprofilelevel4 . 0的高清晰度視頻碼流實時解碼。
  14. Moreover, video control program to implement internal function of fpga is designed including video capture time sequence control, ping - pang frame buffer read and write time sequence control and lcd display time sequence control, and program ' s simulation and analysis is also provided. at last, this paper presents a portable iv ' s video processing system, and proposes three buffer strategy to control capture buffer. and a moving object detection algorithm of combing an adaptive background subtraction technique with a three - frame differencing is adopted

    設計了基於fpga系統結構的車載視頻顯示電路板；利用單片機io口模擬i2c時序，實現了視頻解碼晶元控制；利用fpga實現視頻控制，研究了採集通道時序控制、雙幀存ram讀寫時序控制及lcd顯示時序控制的方法，並進行了軟體模擬和分析；設計了車載視頻檢測系統方案，給出了管理採集緩沖區的三幀緩沖策略，採用綜合三幀差分和自適應背景相減的演算法實現運動檢測，連通體檢測去除虛目標，模擬實驗證明其有效性，同時分析了該演算法在dsp視頻檢測系統中的簡單實現方法。
  15. Since the mpeg - 2 decoding chip is a soc, 32 - bits embedded risc cpu core is used to decode the ac3 and ts bit stream. the risc core is also used to manage the different task in the chip and the video processing unit is realized in asic modules

    論文設計的mpeg - 2系統集成解碼晶元是一個soc ，該soc採用32位嵌入式risccpu核virgo進行音頻ac3和ts流解碼的計算任務，並承擔soc的管理；視頻解碼採用asic實現。
  16. The utilization of high speed dsp can highly increase the performance of anti - interference and anti - detection. the modulation mode, data rate and coding mode can be controlled by configuring the registers of modulator stel - 1109. the viewport and nco frequency control word selection can be accomplished by configuring the demodulator stel - 2105

    Dsp通過i / o讀寫操作，控制調制晶元stel - 1109的讀寫寄存器，用來設置晶元的調制方式、數據速率、編碼方式等；而dsp對解調晶元stel - 2105讀寫寄存器的控制，則對解調的一系列視窗選擇及nco頻率控制字進行了設置。
  17. The pw328 imageprocessor is a highly integrated solution with an internal adc and a video decoder, with an external memory interface to support more advanced windowing capabilities and high - resolution lcd televisions

    Pw328圖像處理晶元是一個高度集成的解決方案，它集成了高速數模轉換、視頻解碼，具有外部存儲介面支持多窗口和高解析度液晶電視能力。
  18. This dissertation discussed a solution of terminal in multimedia communication based on ethernet. and give a reference of constructing a platform of hardware, which consist of embeded cpu based on x86 core and chips of coding video. in linux os, we programmed to realize some functions, to control and change parameters of terminal on live

    本論文討論了一種基於以太網的多媒體通信終端機的設計方案，並給出了一個採用嵌入式x86 +內核的嵌入式處理器加專用視頻編解碼晶元組成的終端機實例，為多媒體通信終端機提供了一種硬體平臺的參考。
  19. The chip of ks0122 is selected for vedio decoding and ad conversion with rgb digital vedio signal output

    其中kso122作為視頻解碼和模數轉換晶元，輸出rob數字信號。
  20. Then a set of remote multimedia surveillance system project based on adv6oilc is provided, and the video matrix switcher and video image processing subsystem are presented expressly. finally, the software design is given

    然後提出了基於adv601lc編解碼晶元的遠程多媒體監控系統的方案，並對視頻矩陣切換電路和視頻圖像處理子系統進行詳細的闡述，並給出相關的軟體設計。
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