觸點邏輯 的英文怎麼說

中文拼音 [chùdiǎnluó]
觸點邏輯 英文
contact logic
  • 觸 : Ⅰ動詞1 （接觸） touch; contact 2 （碰; 撞） strike; hit 3 （觸動） touch 4 （感動） move sb ; sti...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 邏輯 : logic
  1. In addition, a novel heuristic approach which we called “ improved simulated annealing algorithm ” is proposed for bounding maximum and minimum leakage power. 2. a design method for low power clock network is proposed

    通過對高性能通用處理器中時序邏輯特點的詳細分析，提出採用帶門控使能的多比特觸發器設計方法來降低時鐘功耗。
  2. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  3. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  4. The floating - point a / d conversion scheme was employed to increase the system ' s dynamic range. complex programmable logic device ( cpld ) was also used to perform the system ' s function such as data sampling trigger control and data storage control, etc. aduc812, a new type of microprocessor with full a / d converter, was utilized to fulfill the a / d conversion

    在數據採集電路設計中，採用了浮點放大技術來提高系統的動態范圍；通過引入可編程邏輯器件來實現觸發控制、存儲控制；采樣過程中應用了時序重疊技術，從而實現了數據採集系統的流水線作業方式。
  5. While adding new service, the in is functioned by change point of ssp and the service logic of scp instead of the improving of terminating offices and switchers. to meet the requirements of inter - network communication, e - cube fsr216. 3 provides the function of ssp

    智能網在增加新業務時不用改造端局和交換機，是通過業務交換點ssp提供接入智能網的功能，並由ssp通過事件的檢出來觸發業務交換點scp的業務邏輯，從而獲得智能網所提供的各種業務。
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