計數時鐘 的英文怎麼說

中文拼音 [jìshǔshízhōng]
計數時鐘 英文
count clock
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 計數 : count; tally; counting計數卡 numbered card
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. A chronograph is a clock device for recording information according to the time of its occurrence.

    計時儀是一種記錄數據的時鐘儀表，它是按照數據出現的時間加以記錄的。
  2. Such as harmonic distorted in front analog circuit, sample clock shaking, analog power and the noise in ground plane etc. some suggestion of circuit design is given to improve high - speed a / d circuit performance

    在高速模數轉換電路的應用設計中地電源供電設計、模數地平面設計、采樣時鐘設計等方面提出一些具有指導性的意見。
  3. The counter has been preset to 0000 and as the input "runs, " the counter advances by 1 bit per input pulse.

    計數器預置0000，並在時鐘輸入下計算每輸入一個脈沖計數器便累加10。
  4. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  5. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  6. Thirdly, the paper discusses the driver of the peripheral equipment, how to port the uc / os - n and uclinux, h. 323 protocol and the application of the system in the digital speech classroom. also some software and hardware measure are adopted to enhance the system stability. at last, the shortcoming and the something to be improved are given. dsp can be used to realize real - time speech coding algorithm, and after porting ( ac / os - n, arm can manage the keyboard, the lcd and the ethernet peripheral etc. then the embedded network system with specific purpose can be used in others fields, such as pda, set of top, web tv, ect

    在實際設計實現中，為提高系統軟、硬體整體穩定性和可靠性，使用了以下幾種方法： （ 1 ）低電壓復位、抗電源抖動能力、增加時鐘監測電路、抗電磁干擾能力、散熱等技術； （ 2 ）多層pcb設計，線路板結構緊湊，電源部分採用數字5v 、 3 . 3v 、 3v 、 1 . 8v和模擬5v多電源供電； （ 3 ）選用表面貼和bga封裝的器件； （ 4 ）按照軟體工程的要求進行系統分析，規劃系統框圖、流程分析、模塊劃分，減小了不同模塊的相關性，從而最大限度避免了錯誤的發生。
  7. In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail

    文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案，並對其中主要功能模塊和關鍵演算法作出了詳細說明，包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。
  8. Based on these analyses, a more understandable structure of usb was established. secondly, the usb device controller framework was established based on the usb device controller function requirements on clock extracting, protocol layer and data management

    其次，針對usb設備控制器的功能要求，從時鐘提取、事件檢測、協議層、數據處理層通信等方面對其進行了結構設計和詳細設計。
  9. Countdown clocks marking the days until the opening ceremony sprinkle the city and the entire, sprawling metropolis has been turned upside down, with scaffolding covering most of the historical sites, roads being repaved, new highways being built, and construction under way at the actual olympics venues

    倒計時鐘一刻不停地數著距離奧運會開幕還有多少天，諾大的一個北京城都被攪動了起來：多數古跡都「裹著」腳手架進行維護，舊路在修、新路在建，奧林匹克運動場館的建設更是熱火朝天。
  10. The main research contents of this dissertation are shown in the following : ( 1 ) introduce one method of use the counting pulse to develop ie measuring system and new method of using the high frequency clock signal to divide the space pulse

    本文主要研究內容如下: （ 1 ）系統論述了一個脈沖計數方式的ie測量系統的測量原理，闡述了一個採用高頻的時鐘信號細分空間脈沖的新型細分方法。
  11. The key to the fft algorithm is the design of butterfly computation and that of the address logic. the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ), basing on these, we do our research on reconfigurable technology. the result indicates that the data processing ability of reconfigurable system improved greatly

    結果表明，可重構系統在數據處理能力方面比以往的系統有了很大的提高，本設計實現的fft重構處理器可工作於60mhz下，完成一個16點fft需要132個主時鐘周期，完成32點fft需要324個主時鐘周期，而且具有一定可重構性，可以方便地將其運算點數進行擴展，或將其他的圖像處理演算法在實時處理系統中實現。
  12. The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse.

    每當計數器被時鐘脈沖觸發一次時，計數器輸出的二進制數便累減1。
  13. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  14. The developed apparatus can automatically measure evapotranspiration at setting up interval and memory the data through a 32 kilobyte data storage memory. measured data can be transmitted to personal computer by rs232 series communication interface. apparatus will be trigged at measurement time by a real time chip set in it

    該儀器通過實時時鐘晶元實現間隔採集動作的觸發及時間、日期的計數；利用液晶顯示器（ lcd ）進行顯示；使用它能在無人監管的工作環境下，定時進行蒸散測量並將測得數據自動保存到32k數據存儲器中；再通過rs232串列通訊介面將數據傳送到pc機進行進一步處理。
  15. The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation

    再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。
  16. The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse

    每當計數器被時鐘脈沖觸發一次時，計數器輸出的二進制數便累減1 。
  17. One of the most promising new technologies to help achieve that goal is a new breed of low - powered microprocessors that can vary the speeds at which they operate

    在執行復雜的計算任務，如連續處理大批的數字數據時，這種處理器以極高的速度，即"時鐘脈沖速度"運行。但是在執行要求較低的任務，如運行一個文字處理器或放音樂時，該晶元能減速。
  18. A drive method of unequalized clock counter in panel display which uses no dissimilarity @ subclass to achieve precision unequalized clock counter correction based on functions approximation theory is proposed. the new method is acquired based on the particular analysis results of the display drive design projects which adopted counter drive method in which the balance between the display image quality and the cost of drive circuit is given. finally, synthesis comparison examples are given

    針對目前以該方法為基礎普遍採用的不同技術方案進行詳盡的分析，根據分析的結果闡明了其在圖像顯示質量和驅動代價方面的優缺點，在此基礎上基於函數逼近理論提出了一種平板顯示器計數器非均勻時鐘驅動方法，該方法在計數器時鐘上採用非相異子集完成高精度的非均勻時鐘計數器校正。
  19. This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution

    主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。
  20. 2. using the method of dds + pll to generate the system clock and count clock which are synchronous. 3

    2 .通過dds + pll的方法實現脈沖/數據發生器所需的系統時鐘以及計數時鐘的產生，以及其同步的實現。
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