計數譯碼器 的英文怎麼說

中文拼音 [jìshǔyìmǎqì]
計數譯碼器 英文
counting decoder
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 計數 : count; tally; counting計數卡 numbered card
  1. Bcd decode counter

    十進制譯碼計數器
  2. In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework

    另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。
  3. The number of error symbols that can be corrected by the decoder is 2. the design process includes storing the input data, calculating the syndromes, designing multiplier and divider and solving the key equation

    Rs （ 256 ， 252 ）譯碼器的設計過程主要包括輸入數據的存儲、伴隨式的計算、乘法器和除法器的設計、關鍵方程的求解等幾個步驟。
  4. We put the emphases on the soft output viterbi algorithm ( sova ), which is one of turbo code ’ s decoding algorithms, and presents the derivation and computation step of the sova decoding algorithm. after presenting sova and map decoding algorithms and analyzing four kinds of decoding algorithms, the paper makes a comparison among the different decoding algorithms by emulation analysis, and analyzes the time complexity of various algorithms, and then contrasts them. in the last part of this paper, according to the criterion recommended by the consultative committee for space data systems ( ccsds ), including code rate,

    根據空間數據系統顧問委員會（ ccsds ）為turbo碼應用於深空通信系統推薦的標準，包括碼率、碼塊大小、分量碼類型、約束長度、碼生成多項式，以及交織器的選擇等參數的建議以及sova譯碼演算法的理論基礎，設計了sova演算法的實現結構，通過模擬驗證了本文所採用的turbo碼的性能，從而證明turbo碼確實是一種很好的通道糾錯編碼方式，它適用於要求功耗低或信噪比低的深空通信系統中。
  5. In the part, there are following contents : single - chip and memory circuit, interrupt control circuit, decoding circuit, parameter area circuit, watchdog circuit and serial communication interface circuit, etc. in this paper, serial communication interfaces between upper pc and lower single - chips are designed

    其中，微處理器的設計是關鍵。在微處理器部分的設計中，主要包括以下內容：單片機及存儲器電路設計、譯碼器電路設計、參數區電路設計、中斷控制電路設計、看門狗電路設計、串列通信介面電路設計等。
  6. The design and application of ad6640 and ad6624 are fully discussed in this part. the design of software module includes the parameter design for ddc filter and the baseband signal processing of dsp. and the realization of the viterbi channel decoding algorithm by dsp and the simulation of the burst at the transmitter are discussed

    模塊的硬體設計主要包括： a d轉換器、數字下變頻器（ ddc ）以及dsp ，詳盡討論了a d器件ad6640和ddc器件ad6624的設計和應用；模塊的軟體設計主要包括： ddc濾波器參數設計和dsp的基帶信號處理，給出了viterbi通道譯碼演算法dsp實現和發射端突發形成的模擬實現。
  7. This is the core of the issue. in this section we designed the cells of the dac, including the decoder circuit, bandgap reference voltage circuit, current source circuit and switched circuit etc. the fourth chapter the simulations of circuit and errors of the dac are discussedi, so the simulation waveforms are plotted on the paper and we must take the error corrections and minimize ways

    對于整個d a轉換器的具體結構和電路設計放在第三章，這也是本文的核心之處，對d a轉換器的整體電路及主要電路單元如：數字譯碼電路、帶隙參考電壓源電路、電流源產生電路、差分電流開關電路等進行詳細地分析和設計。
  8. The viterbi decoder with hard decision designed by the paper, is aimed at ( 3, 1, 9 ) convolutional coding. the data rate is 9. 6kbps. the data rate received by the rake receiver is spreaded by 127 - bit spread sequences, added pilot signals and modulated by qpsk

    該課題所設計viterbi譯碼是針對（ 3 ， 1 ， 9 ）卷積碼的硬判決譯碼，數據速率為9 . 6kbps ; rake接收機所接收的數據是擴頻因子為127 、加入導頻且經qpsk調制的擴頻信號，使用verilg硬體描述語言在xilinx公司的ise環境下在用現場可編程門陣列（ fpga ）來實現viterbi譯碼器和rake接=收機的功能。
  9. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  10. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。
  11. The circuit design mainly includes interface designs, such as address coding circuit, memory, human - machine, ad converter, the power, etc. the pcb was protracted and tested

    電路設計主要包括譯碼電路設計、存儲器介面電路設計、人機介面電路設計、 ad轉換器電路設計、數控恆流源介面設計等。
  12. Since this decoder has high error - correcting speed and regular structure, it may apply to data transmission and storage to decrease error rate

    由於該譯碼器有較高的糾錯速率和規則的設計結構，使它可以方便地用於數據傳輸和存儲過程中進行差錯控制。
  13. The use of the counter variables in the incrementer classes is a failed attempt to fool the compiler, but compilers are often smarter than we give them credit for when it comes to eliminating dead code

    在incrementer類中使用計數器變量騙不到編譯器，在刪除無用代碼方面我們對編譯器給予了信任，但編譯器比我們想象的還要聰明。
  14. Values. the common practice is to remove the type argument count from the generated code, but the practice is compiler specific

    通常的做法是從生成的代碼中移除類型參數計數，但此做法是特定於編譯器的。
  15. With software and hardware co - design method, this paper proposes an algorithm to calculate register lifetime in programs, and the control of writing results back into rf is implemented through an enable control signal provided by instruction encoding at compile time

    基於軟硬體協同設計的思想，在研究局部變量生存期演算法的基礎上，本文提出了通過編譯器指令編碼實現對硬體結構的使能控制，即控制流水輸出結果是否寫回寄存器文件，以減少對寄存器文件的寫次數，從而降低寄存器文件埠的讀寫壓力。
  16. A design method based on the decomposition and multiplexing technique of complex instruction, combined the decoding arithmetic of instruction and a step counter together, sub - step realization method of multiclocks is proposed. the similarities and differences of architecture between fsm and multi - ? ocks are discussed from two aspects, timing and state space

    提出了執行周期復用的指令分解、指令寄存器與步長計數器聯合譯碼，以及多時鐘同步的控制流設計方法；進而從時間和狀態空間兩個角度深入討論了控制流設計中狀態機和多時鐘兩種常見體系結構的異同。
  17. After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance

    經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。
  18. The two methods, an all - parallel viterbi decoder and an optimized viterbi decoder are represented. the former one is small constrained, simple construction and large resource consuming while the latter one is long constrained, complicated construction and small resource consuming. employing the digital circuit optimize algorithm, the latter one has already covered design thoughts of present viterbi decoder

    對于viterbi譯碼器，描述了適用於小約束度、結構簡單、資源耗費較大的全并行viterbi譯碼器和使用於大約束度、結構復雜、資源耗費較小的優化viterbi譯碼器，其中，優化viterbi譯碼器採用viterbi譯碼優化演算法和數字電路設計的優化演算法，基本已涵蓋了當前viterbi譯碼器的設計思路。
  19. This method fully utilizes the soft outputs of channel coder, and regards it as prior information

    該估計方法充分利用了譯碼器軟輸出中包含的數據的先驗信息。
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