調試程序包 的英文怎麼說

中文拼音 [diàoshìchéngxùbāo]
調試程序包 英文
debugging packaage
  • 調 : Ⅰ動詞1 （配合得均勻合適） harmonize; suit well; fit in perfectly 2 （使配合得均勻合適） mix; adju...
  • 試 : 名詞（古代占卜用的器具） astrolabe
  • 程 : 名詞1 （規章; 法式） rule; regulation 2 （進度; 程序） order; procedure 3 （路途; 一段路） journe...
  • 調試 : shakedown test; debug; debugging
  • 程序 : 1 （進行次序） order; procedure; course; sequence; schedule; ground rule; routing process 2 [自動...
  1. Kylix 3 includes its own means to allow you to test and debug your web applications without apache

    Kylix 3包含自己的一些方法，以允許您（在沒有apache的情況下）測試和調試web應用程序。
  2. In the last part of this thesis, we introduce the component and function of test system, and focus on how to develop the test system in details, include up layer application and device driver, from analyzing to coding. we explain how to develop the gui of test system using photon application builder ( phab ) tools, communicate among processes and schedule the multi - tasks. we also introduce the development of device driver under qnx, include programme of the interrupt handler, management of hardware resource and interface between application and device driver

    首先，以真實的圖形界面為基礎，詳細介紹了測試軟體界面部分的樣式、功能和使用；在此基礎上，進一步介紹了測試軟體編寫中的一些技術細節，如如何使用phab開發圖形界面、如何進行多任務調度、如何進行進程通訊等；最後詳細地介紹了在qnx下驅動程序的開發包括中斷處理函數的編寫、系統硬體資源的管理以及驅動程序與測試程序的介面。
  3. Adopting the method of top - down, the virtual memory is divided into memory mange related unit ( segment unit and page unit ) and protection mode related unit ( protection test unit, debug test unit and exception detect unit ). data buses and control bused are designed separately for all of the units. vhdl codes are written and simulated

    Amex86的虛擬存儲器採用自頂向下的設計方法，把虛擬存儲器劃分為地址管理相關單元（又包括分段單元和分頁單元） 、保護模式相關單元（又包括保護測試單元、調試異常單元利異常檢測單元等） ，分別確立其數據通路和控制通路，完成了vhdl的編碼和模擬工作，通過測試程序模擬驗證了其功能的正確性並測定了基本性能。
  4. High precision ad chip is used for intermediate frequency data sampling and fpga of virtex - series is used for the implementation of intermediate - frequency orthogonal system, which includes the sequencing control design for mult - channel radar system with verilog, the application of ip core of digital filter and fifo, as well as the communication control module with dsp. as the master control part, the software programming for the communication between dsp and fpga is designed. the experimental result with hardware circuit shows the design is valid and practical

    採用高精度的adc晶元完成中頻采樣，通過virtex -系列fpga設計中頻正交系統，主要包括通過verilog語言實現多路雷達中頻接收的時序控制，通過濾波器ip核實現濾波器的設計，以及利用c語言實現dsp的通訊控製程序設計。並給出了fpga在資源和速度上一些優化的方法，調試過程中影響中頻正交接收性能測試的因素。
  5. In the project, the work completed by the author is as followed : ( 1 ) answer for events " transmition, which are transmitted to application programs, and correspondly dealt ; ( 2 ) answer for all of the handware drivers, included lcd display driver, flash driver, e2prom driver, sound driver, gsm status monitorer driver, keyboard driver, uart driver, real - time controller driver, hung - up monitorer driver ; ( 3 ) answer for all problems related with hardware drivers ; ( 4 ) answer for the tools for write data to flash, such as programs, font libraries

    該項目中，本人完成了以下幾方面的工作： （ 1 ）負責所有消息的驅動，使上層應用程序能夠接收到底層硬體設備產生的消息，並做相應處理； （ 2 ）負責所有硬體驅動程序的設計和調試。驅動程序包括lcd顯示驅動、 flash驅動、 e ~ 2prom驅動、聲音驅動、 gsm模塊狀態監控驅動、鍵盤驅動、串口驅動、實時鐘驅動、電源管理、摘掛機檢測驅動，共10部分。 （ 3 ）負責解決遇到的所有與驅動相關的問題。
  6. The structure, function and characteristic with the principle and method of tank gauging system are described. then the structure, principle of the circuit and the main chips of the data processing unit are introduced. after this, the software design of data processing unit including rs - 485 ( modbus ) module, 4 - 20ma analog module, on - off module, rtd module, pulse module, calculation and display module, communication module and neuron chip program module and also the method of resolving the problems which were found at the process of debugging are emphasized

    隨后介紹了現場數據處理器的結構，電路原理，所運用的主要晶元；並重點闡述了作者在課題研究中所作的工作，即現場數據處理器軟體的設計包括八個功能模塊： rs - 485 （ modbus ）模塊、 4 ? 20ma模擬量採集模塊、開關量處理模塊、 rtd信號採集模塊、頻率量採集模塊、計算和顯示模塊、通訊模塊、 neuron晶元中的程序模塊；以及在課題研究和現場調試過程中遇到的問題及解決辦法。
  7. Therefore it comes true the on - line adjusting, real - time control and so on. it sames as real locale. the software of logic protect ( include electric logic ) and control includes some usual algebraic and operation model of thermal control and logic operation of logic protect. it adopts foxboro ' s dcs as a example, so we configuration via filling table, user only define i / o condition, fill certain operation variable, and name logic variable. the software offers a friendly user ' s interface, personnel can compile and modify the control and logic program, change the value of logic and control variable conveniently, attach themselves to run, debug and control the set, not need to know about the inside of the old programs deeply. so the configuration software offer a flat that control engineer can attend to the structure of control loop and logic protect ( include electric logic ), not but to handle complicated program

    它以foxboro的dcs控制系統為主要參考模式，採用填表的方式進行控制組態，用戶只需定義i / o條件、填寫具體的運算變量名、邏輯變量名即可。本軟體為建模人員提供了一個友好的用戶界面，使建模人員在建模時不必對模塊內部的控制、邏輯程序有很深的了解就可以方便的對其進行編寫和修改，實時改變各邏輯和控制變量在數據庫里的值，參與運行和調試，從而實現對機組的控制。因此，本組態軟體提供的這樣一個平臺，讓控制工程師能集中精力于控制迴路及邏輯保護（包含電氣邏輯）的構成，而不必拘泥於一些具體而煩瑣的程序操作。
  8. The concrete steps include the design of schematic, the design and optimization of printed circuit board, the manufacture and debugging of hardware, the program and debugging of eprom software, the design and embedding gal devices

    具體過程包括設計通信卡的原理圖；設計和優化印刷電路板圖；硬體製作和調試；編寫及調試eprom程序；設計及燒寫gal器件邏輯等。
  9. Efw software design mainly includes programming of bootloader, efw card drive, and efw package filtering ; the transplant of uc / os - ii. the implement of efw has been tested in lan environment, and it is able to filter the data in and out of efw network card according to the security strategy defined by the program

    Efw核心軟體設計及實現主要包括bootloader程序的編寫與調試; uc / os - ii嵌入式操作系統的移植; efw網卡驅動程序的編寫與調試; efw包過濾程序的編寫與調試等工作。該嵌入式防火墻在局域網環境中進行了測試，它能夠根據程序中定義的安全策略對進出efw網卡的數據進行過濾。
  10. The linux kernel components stressed with this benchmark include the scheduler, signals, and tcp ip

    該基準測試程序所著重的linux內核組件包括調度程序、信號和tcp / ip 。
  11. The five main sections of this thesis are as follows : 1 ) component parts and working flow of intelligent community 2 ) hit communicating protocol 3 ) technical points of hardware design single chip micro - controller touch screen rf data transmitting identification confirmation flash memory 4 ) software design under avr studio3. 53 ide 5 ) method and result of system test

    論文包括以下幾個主要部分： 1 ）智能小區系統組成及系統運行流程2 ） hit通信協議3 ） hit - 5終端硬體電路設計單片機技術觸摸屏輸入技術無線數據收發技術身份識別技術flash存儲技術4 ） avrstudio3 . 53程序設計5 ）系統測試方法及調試結果
  12. The main subject including : the constructure of this mpeg2 encoder ; ~ the principle and the system of tv, also the determination of tv signal ? pcm parameter and the international standard of video pcm ; ? he protocol of pci and the driver of pci device ; the hardware & software design of some corresponding interfaces of mpeg2 encoder, allowing for the working condition, there is some discussing on programming of mater control ; debugging and testing

    主要內容包括： mpeg2編碼器的體系結構；電視原理、制式以及電視信號的pcm編碼參數的選擇和pcm編碼的國際標準； pci總線協議標準及pci設備驅動程序的編寫； mpeg2編碼器的相關介面的具體硬體設計和相應的軟體設計，結合具體情況，討論了主控編程；硬體調試。
  13. Explore various methods for debugging php applications, including turning on error reporting in apache and php, and by placing strategic print statements to locate the source of more difficult bugs through a simple example php script

    本文介紹調試php應用程序的各種方法，包括在apache and php中打開錯誤報告，以及通過在一個簡單的php腳本中放置策略性的print語句，找到更困難的bug的源頭。
  14. The task in the paper comprises two parts. the software design procedure works as follow, program the drivers for module on pc with cvi, generate the corresponding ddl and then edit the test serial and invoke the ddl by designing soft panel with vc + + 6. 0. thus facilitate users to control module to conduct high speed data test. the hardware design procedure works as follow, design vxi message based interface circuit and plesio - fdc circuit with fast data transport function on xc2vp30, a virtex - ii pro series fpga chip designed by xilinx company which integrates power - pc processor

    筆者負責的工作包括軟體設計和硬體設計兩部分:軟體設計是用cvi工具編寫模塊在pc機上的驅動程序，生成動態連接庫，再用visualc + + 6 . 0設計軟面板，實現測試矢量的編輯和動態連接庫的調用，讓用戶很方便地控制模塊進行高速數據測試;硬體設計是在xilinx公司的一片集成了power - pc處理器的virtex - iipro系列fpga晶元xc2vp30上完成vxi總線的消息基介面電路設計和具有快速數據傳送功能的準fdc電路[ 1 ] [ 2 ]設計。
  15. According to the definitions of bottleneck bandwidth, available bandwidth and bulk transfer capacity, we analyzed the algorithms which named vps ( variable packet size ), pptd ( packet pair / train dispersion ), slops ( self - loading periodic streams ) and topp ( trains of packet pairs ) ; based on the principle of sub - path bottleneck measurement, we developed the bottleneck measurement algorithm using heterogenous packet - pair train ; after designing the three child algorithms ( demarcating bandwidth range, approaching bandwidth value and predicting the trendency of available bandwidth fluctuation ), we performed the algorithm called self - loading binary search ; applying the multi - home properties of sctp ( stream controltransmission protocol ) and measurement algorithm of available bandwidth, we presented a scheme to adjust the sctp transport path when there are network congestions or faults ; by the library of winsock and winpcap, we developed a measurement program to look for bottleneck bandwidth. in ns2 experiments, the algorithm based on heterogenous packet - pair train fitted well, and the algorithm of self - loading binary search worked quickly, and the sctp scheme improved the throughput effectively

    本文根據瓶頸帶寬、可用帶寬和btc （ bulktransfercapacity ）三類網路帶寬定義，分析了vps （ variablepacketsize ）和pptd （ packetpair / traindispersion ）瓶頸帶寬測試演算法， slops （ self - loadingperiodicstreams ）和topp （ trainsofpacketpairs ）可用帶寬測試演算法;基於子路徑瓶頸測試原理，設計了異構包對序列的瓶頸測試演算法;並結合三個子演算法（界定帶寬范圍演算法、接近帶寬值演算法和帶寬變化趨勢判定演算法） ，設計了自載流折半查找的可用帶寬測試演算法;把上面的演算法應用到sctp （ streamcontroltransmissionprotocal ）的多宿性和可用帶寬測試，提出了一個網路擁塞或故障時調整sctp傳輸路徑的方案;結合winsock和winpcap兩套網路開發工具，設計了一個瓶頸帶寬測試程序;通過ns2模擬實驗，驗證了基於異構包對序列瓶頸測試演算法的準確性、自載流折半查找演算法的快速性，和sctp改進方案的有效性。
  16. Automatic docking is one of the most important actions for msr robot ’ s self - reconfiguration and is one of the technologys about the robot researching, because it supports almost all practical advantages of such robot. in this thesis, automatic docking system and the module structure are first analyzed ; for searching the reason why the actual docking system run unsteadily, some validate and test thing are done, such as docking algorithm test, sensor unit test, drive unit test, and so on

    自動對接是模塊化自重構機器人完成自重構的一個基本步驟，也是這種機器人研究的關鍵技術之一，是模塊化自重構機器人具有實際應用價值的基礎。本文對自動對接系統結構進行了分析，為尋找實際對接系統工作不穩定的原因，做了一些驗證與調試方面的工作，包括自動對接演算法正確性與有效性的驗證，串口電路設計，編寫實時跟隨對接模塊運動的程序以及傳感器建模程序等。
  17. You can include an exception in a trace record if you are using tracing to debug an application or troubleshoot error and exception handling

    如果您正使用跟蹤來調試應用程序或排除錯誤和異常處理，則可以在跟蹤記錄中包含一個異常。
  18. Lei now includes sym files for the windows 32 platform, which will improve the likelihood of fixes being delivered without first installing debug code

    現在， lei包括了用於windows 32平臺的sym文件，這將使得無需首先安裝調試代碼即可分發修補程序的可能性更大。
  19. The main work of this thesis is as follows : firstly, the display principle of tft - lcd is expatiated ; secondly, test software for tft - lcd module is written, including tft - lcd module interface programme, tft - lcd test programme, touching panel driving programme and gui ( graphics user interface ) programme ; thirdly, test software is debugged and analyzed ; finally, optics characteristics and electric characteristics of standard tft - lcd module are tested by this test software, and tested data are analyzed

    二、 tft - lcd模塊測試軟體設計，具體包括tft - lcd模塊介面程序程序設計、 tft - lcd測試程序設計、觸摸屏程序設計以及圖形用戶界面程序設計。三、對測試軟體進行調試分析。四、採用測試軟體對標準的tft - lcd模塊的光學特性和電氣性能進行測試，並分析比較所測得的數據。
  20. The event handler for the test procedure stack button contains code to call several methods resulting in a stack several levels deep

    「測試過程堆棧」按鈕的事件處理程序包含用於調用多個方法的代碼，這些方法導致堆棧出現多層深度。
分享友人
分享到 Line

分享到臉書