譯碼器電路 的英文怎麼說

中文拼音 [yìmǎqìdiànlù]
譯碼器電路 英文
decoder circuit
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. Bcd detail specification for electronic component. semiconductor integrated circuit. type ch2019 4 - line to 10 - line decoder with bcd - in

    電子元器件詳細規范.半導體集成電路ch2019型4線- 10線譯碼器
  2. Each unit is extracted from the circuit, and is analyzed detailedly in framework, configuration and design approach. the instruction system of c9821 is unscrambled and then the instruction decode algorithm are obtained. the complete program of c9821 including basic arithmetic and root square operation is realized

    在軟體方面，破譯了c9821的指令系統，分析了指令譯碼電路的設計技術，分析了計算器內bcd碼的四則運算及開方運算演算法，得到了實現c9821全部功能的程序，掌握了該計算器的程序設計方法。
  3. In the part, there are following contents : single - chip and memory circuit, interrupt control circuit, decoding circuit, parameter area circuit, watchdog circuit and serial communication interface circuit, etc. in this paper, serial communication interfaces between upper pc and lower single - chips are designed

    其中，微處理器的設計是關鍵。在微處理器部分的設計中，主要包括以下內容：單片機及存儲器電路設計、譯碼器電路設計、參數區電路設計、中斷控制電路設計、看門狗電路設計、串列通信介面電路設計等。
  4. This is the core of the issue. in this section we designed the cells of the dac, including the decoder circuit, bandgap reference voltage circuit, current source circuit and switched circuit etc. the fourth chapter the simulations of circuit and errors of the dac are discussedi, so the simulation waveforms are plotted on the paper and we must take the error corrections and minimize ways

    對于整個d a轉換器的具體結構和電路設計放在第三章，這也是本文的核心之處，對d a轉換器的整體電路及主要電路單元如：數字譯碼電路、帶隙參考電壓源電路、電流源產生電路、差分電流開關電路等進行詳細地分析和設計。
  5. The whole circuit includes memory array, decode, sense amplifier, data in - out circuit and pre - charge circuit

    電路包括存儲陣列、譯碼電路、敏感放大器、數據輸入輸出電路，預充電電路等部分。
  6. An application of logic devices able to program to the decoding circuit

    可編程邏輯器件在譯碼電路中的應用
  7. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  8. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。
  9. Audio codec requirements for the provision of bi - directional audio service over cable television networks using cable modem

    使用電纜數據機通過有線電視網路提供雙向音頻服務的音頻編碼譯碼器要求
  10. The circuit design mainly includes interface designs, such as address coding circuit, memory, human - machine, ad converter, the power, etc. the pcb was protracted and tested

    電路設計主要包括譯碼電路設計、存儲器介面電路設計、人機介面電路設計、 ad轉換器電路設計、數控恆流源介面設計等。
  11. The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit

    硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。
  12. In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl

    在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖，包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹，闡明了使用hdl語言設計超大規模集成電路的一般特點。
  13. The down - up design includes the researches of decoder schematics, controller schematics, pipeline schematics, bus schematics, stack schematics and interrupt schematics. the thesis content and outcome of research are beneficial to the design of a cpu design project. at the same time, these contents are beneficial to the design of a microcontroller

    整個正向設計由於採用了簡化的措施，還存在一些不足，因此從逆向設計的角度，研究了pic微控制器晶元中處理器的電路實現結構，主要包括譯碼電路和控制器電路的實現結構，流水線電路的實現結構，處理器內總線的實現結構，以及堆棧和中斷電路這些與處理器電路有密切相關性的子電路單元。
  14. Detail specification for electronic components. semiconductor integrated circuit ct54ls138 ct74ls138 3 - to - 8 line decoder

    電子元器件詳細規范.半導體集成電路ct54ls138 ct74ls138型3線? 8線譯碼器
  15. Bcd detail specification for electronic component. semiconductor integrated circuit - cc4028 cmos 4 - line to 10 - line decoder with bcd - in

    電子元器件詳細規范.半導體集成電路cc4028型cmos 4線? 10線譯碼器
  16. Detail specification for electronic components. semiconductor integrated circuit ct5442 ct7442 4 - line - to - 10 - line decoder bcd - to - decimal

    電子元器件詳細規范.半導體集成電路ct5442 ct7442型4線- 10線譯碼器bcd輸入
  17. Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology

    然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
  18. The two methods, an all - parallel viterbi decoder and an optimized viterbi decoder are represented. the former one is small constrained, simple construction and large resource consuming while the latter one is long constrained, complicated construction and small resource consuming. employing the digital circuit optimize algorithm, the latter one has already covered design thoughts of present viterbi decoder

    對于viterbi譯碼器，描述了適用於小約束度、結構簡單、資源耗費較大的全并行viterbi譯碼器和使用於大約束度、結構復雜、資源耗費較小的優化viterbi譯碼器，其中，優化viterbi譯碼器採用viterbi譯碼優化演算法和數字電路設計的優化演算法，基本已涵蓋了當前viterbi譯碼器的設計思路。
  19. Then, the author specially studies the characteristic of system architecture of the dsp, paints schematic principle diagram and pcb diagram of the hardware circuit system, writes the program decoding and partial data processing of the cpld, adopting verilog hdl hardware describing language

    然後，研究了dsp晶元結構體系的特點，繪制了硬體電路系統的原理圖和pcb圖，且採用veriloghdl硬體描述語言編寫了復雜可編程邏輯器件（ cpld ）的譯碼與部分數據處理程序。
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