路由器標識 的英文怎麼說

中文拼音 [lùyóuqìbiāozhì]
路由器標識 英文
router distinguisher
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 由 : causereason
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 標 : Ⅰ名詞1 [書面語] （樹梢） treetop; the tip of a tree2 （枝節或表面） symptom; outside appearance; ...
  • 識 : 識Ⅰ動詞[書面語] （記） remember; commit to memory Ⅱ名詞1. [書面語] （記號） mark; sign 2. （姓氏） a surname
  • 路由器 : brouter
  • 標識 : [物理學] characteristic; identification; identifying標識碼 identification code; 標識位置 home position
  1. As it ' s proprietary, a large numbers of bibliography resource ca n ' t be provided to common readers of internet. along with the development of network technology, it has a instancy need to conversion marc format to the information that the browser can recognize. the language xml not only can expresses the metadata, but also can show the content of data. lt can provide individuation page layout

    Marc格式是目前圖書館館藏資源的主要表示格式，由於其專用性，使得目前大量的書目資源無法通過一般的搜索引擎向internet用戶提供，隨著網路技術的不斷發展，迫切需要將marc格式的數據轉換成常用瀏覽器所能識別的信息，為大眾提供服務，可擴展標記語言xml不僅可以表達元數據，而且可以揭示數據的內容，提供個性化的頁面顯示，用xml語言對marc數據進行描述是解決這一問題的有效途徑，文章提供了marc數據的xml表示方法和實現途徑。
  2. As the scheme of packet distributed influence the performance of parallelism, in this paper, the hdw ( hash - based dynamic weight ) scheme for allocation packets in network processors is presented. the scheme is building and keeping one mapping relationship between packets ’ identifier and pes in a table of hash. the mapping formula is derived from the hrw ( highest random weight ) scheme, it is complemented by a feedback control mechanism designed to monitor processor ’ s utilization

    由於報文分配策略影響網路處理器并行性能，我們提出了hdw （ hash - baseddynamicweight ）負載分配演算法，基於報文流標識與pe間建立映射關系，並將映射關系保存在哈希表中，映射關系基於hrw （ highestrandomweight ）演算法，增加了負載反饋迴路監控pe負載狀況，通過動態調整策略阻止pe間負載偏差。
  3. However, because of the low speed of program operation and the invalid blocks of flash memory, if we want to make it the storage medium of solid state recorder on the spacecraft, several problems need to be resolved : 1 ) how to improve the speed of program and erase operation of flash memory ; 2 ) how to map out and bypass the invalid blocks and effectively manage the mass memory space

    但是由於flash的寫入（編程）速度慢、存在無效塊等問題，使要將其應用於星載大容量存儲器，亟待解決以下幾個問題： （ 1 ）如何有效地提高閃存的編程和擦除速度； （ 2 ）如何標識和旁路初始和使用過程中出現的無效塊，並有效地管理大容量數據存儲器。
  4. After analyzing the characteristic of the parallel processing system, some problems about design missile - carrying processing system are pointed out ; network in the parallel processing system has become bottleneck and affect the performance of system, so the processing efficiency is analyzed in a multiprocessor system based on cluster - bus and some rules in designing the network in the multiprocessor system are brought out ; genetic algorithm is used for scheduling in the multiprocessor system, and a scheduling algorithm is described to suit arbitrary number of tasks, unequal task processing time, arbitrary precedence relation among tasks and arbitrary number of parallel processor, so that the schedule length will be minimized ; finally, an atr algorithm is mapped to a ring multiprocessor system, and a block diagram using dsp device is constructed. in chapter 4, the study is performed on real - time system hardware realization of atr. tms320c80 is selected as the kernel processor in multiprocessor system

    為此，對一種由常用的dsp晶元組成的多處理器系統的處理器利用率進行了分析，提出了多處理器系統互連網路設計的基本原則；本章使用遺傳演算法作為實現多處理器調度的工具，提出了一種新的任務調度演算法，該演算法主要是為了解決在任務數任意、任務計算時間不相等、任務前趨關系任意、以及任務間存在通信和考慮任務存貯器要求的情況下，如何優化任務在各個處理器上的分配和執行順序，使得多處理器系統總的執行時間最小；最後對一個目標識別演算法進行了硬體實現優化分析，根據分析結果，將演算法映射到由dsp晶元組成的環形網路連接的處理器拓撲結構上，得到了多處理器系統的原理框圖。
  5. The thesis is composed of 9 parts : the background, significance, main topics and innovations in the thesis are introduced in chapter 1 ; in chapter 2, the main function and performance of interface circuits are described from the view of system by using the example of gigabit ethernet ' s transceiver ; the transmission media ' s frequency characteristics and model are analyzed for the high - speed data transmission system in chapter 3 ; the line driver is presented in chapter 4 ; the equalization principles for high - speed data transmission system are introduced in chapter 5 ; a novel adaptive equalizer for 1000base - cx transceiver is presented in chapter 6 ; in chapter 7, a fixed equalizer for 2. 5gbps transceiver is described ; in chapter 8, layout design and measured results are discussed ; at last, the conclusions are drawn in chapter 9. during period of finishing the thesis, i read lots of literatures about the interface circuits in high - speed data transmission system, studied their principles and design techniques, and designed : 1 、 the line driver for 2. 5gbps baseband copper cable transceiver ; 2 、 the fixed equalizer for 2. 5gbps baseband copper cable transceiver ; 3 、 the fixed equalizer for 1. 5gbps sata ( serial at attachment ) transceiver ; 4 、 an adaptive equalizer for 1000base - cx transceiver

    論文由9部分組成：在第一章引言中介紹了論文的背景、意義、國內外研究現狀，以及論文的主要內容和創新；第二章以千兆位以太網為例，從系統的角度介紹了高速數據傳輸系統介面電路的主要功能和性能指標；第三章分析了高速數據傳輸系統的傳輸介質的頻率特性和模型；第四章描述了線驅動器的設計原理及其電路實現；第五章描述了高速數據傳輸系統的均衡原理；第六章描述了適用於1 . 25gbps基帶銅纜收發器系統的自適應均衡器的設計原理和電路實現；第七章描述了適用於2 . 5gbps基帶銅纜收發器系統和1 . 5gbps串列硬盤介面（ sata ）收發器系統的固定均衡器的設計原理及其電路實現；在第八章中分析了電路的版圖設計及晶元測試結果；最後，第九章總結了全文。在完成論文期間，查閱了大量的有關高速數據傳輸系統介面電路方面的文獻，較系統地學習了線驅動器、傳輸線和均衡器等方面的理論知識和電路設計原理，設計了用於： （ 1 ） 2 . 5gbps基帶銅纜收發器系統的線驅動器； （ 2 ） 2 . 5gbps基帶銅纜收發器系統的固定均衡器； （ 3 ） 1 . 5gbpssata系統的固定均衡器； （ 4 ） 1 . 25gbps基帶銅纜收發器系統的自適應均衡器。
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