通信寄存器 的英文怎麼說
中文拼音 [tōngxìnjìcúnqì]
通信寄存器
英文
communication register-
The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data
具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。Also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals
搭建了一個驗證系統，通過單片機來配置初始化寄存器和控制寄存器的值來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。These allow you to stop at procedure locations, inspect memory and register values, change variables, observe message traffic, and get a close look at what your code does
這些功能使您可以在某些過程位置停止執行，檢查內存和寄存器值，更改變量，觀察消息通信量，以及仔細查看代碼的行為。In the part of voice encryption, spatiotemporal chaotic system ( ocoml model ) and lfsr are used to generate multidimensional pseudo - random sequence. this sequence has a longer period, better randomicity, passing the verification of fips 140 - 2 security requirements. using the key stream generated by it to encrypt the voice gets a better security
在語音加密方面，本文利用時空混沌系統（單向耦合映象格子模型）與線性移位寄存器產生了高維的偽隨機序列，該序列周期很長，具有更強的隨機性，通過了fips140 - 2的安全性能驗證，利用其作為密鑰流對語音信號進行加密，獲得了更高的保密性。The bus is programable. at this rate the user can program the mcu firmware to configure the correlative registers before using the bus. the user can also change the bus channel in the gpmb when the data of different type is to be transfered. in conclusion, gpmb module provides the communication channel between usb2. 0 ip core and peripheral
它提供32位可編程介面，用戶可以通過usb2 . 0ip核中的mcu固件對內部相關寄存器進行配置來使用這32位總線，並可以在內部的多總線通道中切換，以達成usb2 . 0ip核對外圍介面的控制及數據傳輸，進而完成設備通過usb2 . 0介面ip核與主機通信的功能。Within this scope, users can get almost any frequency clock by configuring the register, as the tune - process is nearly continual ( in fact there are many discrete frequency points ). the main circuit of the clock generator is a cppll ( charge pump pll ) designed in a method
該時鐘發生器可以向系統提供頻率范圍是93 . 75k - 180mhz的時鐘信號，用戶可以通過配置寄存器的方法使時鐘發生器輸出自己需要的頻率，而且這一調頻過程幾乎是連續的（實際上是眾多離散點構成的線性近似） 。This text introduced the work patterns and register structure of 80386 processors in detail at first, latterly expounded especially the hardware interrupt handling of windows 98 with the course to the kernel of windows 98 ; then recommended the framework of realization of highly demanding hardware board interrupt handling by revising idt to intercept interrupt handling at hardware layer, subsequently introduced the application and development of vxd technology to achieve interrupt handling overall all situations under the windows 98 platform ; finally introduced the b / s pattern network application development part of this topic, specifically introduced the jsp technology system, elaborated the communication between network application part and the hardware interrupt handling routine combined with the jni technology, and provided partial important program and corresponding commentary
本文首先詳細介紹了80386處理器的工作模式和寄存器結構，接著對windows98的內核進行了相關分析，重點介紹了windows98的硬體中斷處理過程;隨后介紹了通過修改中斷向量表以實現在硬體層截獲中斷來實現高實時性處理的框架，又介紹了windows98下虛擬設備驅動vxd技術的應用與開發，以及中斷全局處理的實現;最後介紹本課題的b / s模式網路應用開發部分，具體介紹了jsp技術體系，並結合jni技術闡述了網路應用與硬體中斷處理程序的通信，並給出部分關鍵程序及其注釋。H. 323 is the standard about multimedia communication released by itu - t. tm1300 including a very powerful, general - purpose vliw processor core ( the dspcpu ) that coordinates all on - chip activities is a media processor for high - performance multimedia applications that deal with high - quality video and audio. the dspcpu implements a 32 - bit linear address space and 128, fully general - purpose 32 - bit registers
H . 323是itu ? t推出的用於ip分組網路的多媒體通信終端協議， trimediatm1300處理器晶元是philips公司推出的一種基於多媒體應用的具有vliw指令，含有128個通用寄存器， 32位的高性能處理器，它能夠通過編程實現通信協議，完成高質量的音頻、視頻處理和網路介面。Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment
Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。Home location register ( hlr ), where the important data of all mobile subscribers in its donation area is stored, is the central database of mobile telecommunication system. therefore, the security of data in hlr plays an important role
移動通信的蓬勃發展，需要高性能、大容量的移動通信系統，這對gsm移動通信網中心數據庫的歸屬位置寄存器（ hlr ）系統提出了新的要求。As an important database of cdma moving communication system, home location register system ( hlr ) mainly stores and affords the locations of moving terminal users and supplies scrvice information. in a word, it is the core of the information recorded in the system
歸屬位置寄存器hlr （ homelocationregister ）作為cdma移動通訊系統中的一個重要數據庫，主要存儲和提供移動終端用戶的位置信息和業務信息，是cdma系統的核心。A switch ic for analog signal processing is designed and implemented, which can fulfill the functions of sampling, weighting, controlling and summing of high frequency analog signals. the circuit consists of three parts : four channel analog switches, a voltage reference and the control circuitry. each analog switch is comprised of two high - transconductance n - mosfets with high w / l ratio, which realize the fine tuning and coarse tuning of the input signal respectively
本文研究並設計了一種可對高頻信號進行取樣、加權、控制、疊加的模擬信號處理丌關集成電路，它包括模擬開關、電壓基準源和移位寄存器三個功能模塊，通過兩個高寬長比的高跨導nmos晶體管實現權值的粗調和微調。The configure file is downloaded into the fpga chip according to the fpga design fl ow. also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals
使用xillinx的fpgaxc2550pq208 ，經過fpga的實現流程，把配置文件配置到xczs5opqzos ，搭建了一個驗證系統，通過單片機來對各控制寄存器寫入控制字來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。The a / d and cap circuits on dsp sample the voltage and current signals coming from the signal sampling circuit and the speed signal of the motor respectively. the " dead time " register of the dsp prevent directive - through of the igbts on the up and the down bridge arms
利用dsp上的死區寄存器設置ipm驅動信號的死區時間防止上下橋臂igbt的直通；利用板上集成的a / d轉換器採集經過板級外圍電路處理的電路信號；利用板上的捕獲單元cap採集通過轉速計的輸出從而得到電機的轉速。Information is transmitted to and from registers via buses.
信息是通過總線輸入寄存器或由寄存器輸出的。分享友人