通用邏輯元件 的英文怎麼說

中文拼音 [tōngyòngluóyuánjiàn]
通用邏輯元件 英文
universal logic element
  • 通 : 通量詞（用於動作）
  • 用 : Ⅰ動詞1 （使用） use; employ; apply 2 （多用於否定: 需要） need 3 （敬辭: 吃; 喝） eat; drink Ⅱ名...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 件 : Ⅰ量詞（用於個體事物） piece; article; item Ⅱ名詞1. （指可以一一計算的事物） 2. （文件） letter; correspondence; paper; document
  • 通用 : be in common use; be current; apply or be used universally
  • 邏輯 : logic
  1. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  2. Secondly, the composition and function of expander board is introduced, the paper describes a detail developing process of selecting component, design interface circuit, protract pcb with protel and design pci interface logic and user ' s logic. with ahdl and max + plus. in addition this paper discusses how to debug pci board, and give the simulation waveform and the result of debug. on the base of all functions is ture, this paper introduce the config registers and memory of bu - 61580, realize the interrupt function and communication based on mil - std - 1553b

    首先分析了擴展板的組成、功能，對pci介面邏輯和擴展板的內部邏輯進行詳細設計，並根據其資源要求進行器件選擇，然後使用protel工具進行電路板的製作。另外，本文還介紹了擴展板的調試方法，給出了邏輯模擬波形和調試結果。在此基礎上，本文闡述了協議晶元的配置方法，實現了1553b通訊擴展板間的通訊及中斷功能，達到了開發技術指標。
  3. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  4. A design ot portable digital oscillograph based on dsp is presented. a integrated prototype is composed of high speed data processing module by which signal is digitalized, data processing unit whose core is dsp, general controller as which cpld is used and terminal facility - - lcd

    通過高速數據採集模塊將信號數字化，以高性能數字信號處理器tms320vc5402為核心構成數據處理單元，採用高密度的可編程邏輯器件epf6016a設計儀器的系統控制單元，使用液晶顯示器做為終端顯示設備，構成一個完整的示波表樣機。
  5. 4. through using the concept of logic balance, a high performance telecommunication switch network test chip is accomplished by using xilinx virtex 300e - 6 and the working clock frequency is up to 125mhz. this chip can give an exact test for the network delay time, throughput, network delay time dither, rate of errors and lost data

    4 ）結合邏輯平衡的思想，採用xilinxvirtex300e - 6器件，為一家著名的通訊技術有限公司設計了速度達125mhz的交換網測試晶元，能夠對交換網的吞吐率，網路延時，網路延時抖動，數據包錯誤率，包丟失率等進行嚴格的測試，並根據當前網路的流量大小自動調節網路負載。
  6. According to the basic theory of iir filters, a scheme of hardware implementation is worked out combining with the fact that coefficients of numerator and denominator of transfer function are fixed and the structural feature of selected hdpld. from the clew of implementing a stratified ， modularized and parameterized design ， the thesis describes the hardware implementation of the iir filter with vhdl and schematic diagram design method. two examples that are iir notch filter and iir low - pass filter are given ， the stability of filters and the effects of quantification of coefficient are also analyzed

    以iir數字濾波器的基本理論為依據，結合濾波器的傳遞函數分子、分母系數固定這一事實和選用的高密度可編程邏輯器件的特點，確定了iir數字濾波器的硬體實現方案；按照層次化、模塊化、參數化的設計思路，採用vhdl硬體描述語言和原理圖兩種設計技術進行了iir濾波器的硬體設計；本文給出了iir陷波濾波器和低通濾波器兩個設計實例，對設計的濾波器都進行了穩定性分析和系數量化影響分析；最終將完成的iir濾波器的硬體設計配置到晶元中，並在製作的實驗電路中進行了實際濾波效果測試。
  7. In hardware design, an integrated multi - center a / d chip is for input signal conversion, cpld and arm empu are the core of fault diagnosis system and information processing. host computer is connected with the system through network technology - which owns certain advantages such as wide range of input signal, powerful processing ability and low power consumption ; also it can be extended as a remote portable terminal

    在硬體設計上，採用集成多通道a / d轉換晶元完成輸入信號的轉換，使用大規模可編程邏輯器件和高性能嵌入式處理器作為故障診斷系統控制和信息處理的核心，採用網路技術實現診斷系統與主機的連接，系統具有前端輸入信號范圍寬，處理能力強，功耗低，可擴展為遠程診斷系統便攜式終端等優點。
  8. At last, the bit file is downloaded into the device through jtag interface and the function of the device is verified by online logic analyzer chipsocpe

    最後，將位流文件通過jtag介面下載到晶元中。並使用在線邏輯分析儀chipscope對下載后的器件的功能進行了在線驗證。
  9. The design of cdma terminal chip is a very actual value and extensive application problem in the field of cdma technology application. with the development of micro - electronics technology, the design of integrated circuit has stepped into the age of soc ( system on chip ), which provide a brand - new method for cdma communication system project. in this paper, a design of cdma2000 1x spread modulation soc has be researched with large scale field programmle gate array device, and make a certain results

    Cdma終端晶元設計是cdma技術應用領域中一個具有重要實際應用價值和廣闊應用前景的研究課題。隨著微電子技術的發展，集成電路設計進入了片上系統時代，這為cdma移動通信系統設計提供了一個全新的技術手段。本文將基於cdma技術，用大規模可編程邏輯器件對第三代移動通信cdma20001x的擴頻調製片上系統設計做了進一步的探討和研究，並取得了一定的成果。
  10. In this solution, the embedded soft cpu ip core is used as the kernel digital module with its periphery controllers based on residual les. in addition, analog channel circuit is added to form an integrated dso system. this dissertation focuses on framework construction, gui design, memory management, message fifo management, other hardware drivers and describes design and implementation of software simulation system written in advanced languages

    在這種方案中，使用了在fpga中嵌入cpu軟核作為控制核心，並用fpga晶元中剩餘的其他可編程邏輯資源構成該嵌入式系統的外圍器件，形成數字示波表的數字核心模塊，並配以模擬通道部分電路，組成了一個完整的數字示波表。
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