通用邏輯門 的英文怎麼說

中文拼音 [tōngyòngluómén]
通用邏輯門 英文
ulg universal logic gate
  • 通 : 通量詞（用於動作）
  • 用 : Ⅰ動詞1 （使用） use; employ; apply 2 （多用於否定: 需要） need 3 （敬辭: 吃; 喝） eat; drink Ⅱ名...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 門 : Ⅰ名詞1 （房屋、車船等的出入口 ） entrance; exit; door; gate 2 （形狀或作用像門的東西） switch; va...
  • 通用 : be in common use; be current; apply or be used universally
  • 邏輯 : logic
  1. At the same time, it also illustrates the superiority of this kind of communication by introducing the profibus field bus. take the transformation of focke packaging machine as an example, the main content is as follows : 1st, to analyze the plc control system of s5 series, and determine the concrete functions that the new plc control system hopes to achieve as well as how to achieve the goal through studying the work program of the original one ; 2nd, to demonstrate the advantage of the field bus in the process of digital alternation by introducing the principle agreement of field bus profibus ; 3rd, to achieve each function of the original control system through using siemens ' s plc control system in the design of hardware and step 7 in the software as well as designing and compiling control system of focke packaging machine ; 4th, to use fm455 for controlling temperature not only can meet the system ’ s severe request for temperature and efficiently avoid many demerits of the temperature control instrument but also can bring convenience for operation and maintenance ; 5th, to use the intouch configuration software to compile monitor and control program can accomplish the goal for real - time surveillance and control of the production line, while setting some parameters can provide a powerful alarming function

    以改造focke包裝機為例，主要內容如下: 1 、通過熟悉原有控制系統的工作流程，分析了原s5系列可編程邏輯控制器的控制系統，確定新的可編程邏輯控制器控制系統需要實現的具體功能以及其實現方法; 2 、在本系統數據交互中，通過介紹profibus現場總線原理協議，論述了現場總線在工業通訊中的優點; 3 、下位機硬體設計上使用西門子可編程邏輯控制器控制系統，軟體平臺採用西門子step7 ，設計和編制了focke包裝機控制軟體，實現了原有控制系統的各項功能; 4 、本系統對溫度要求嚴格，採用溫控儀表控制溫度不能滿足系統要求，而且溫控儀表操作和維護都不方便，因此採用fm455溫度控制模塊進行溫度控制，滿足了系統對溫度的要求，同時又有效地避免了溫控儀表在操作和維護上的缺陷; 5 、在監控系統上，使用intouch組態軟體設計了系統的監控界面，從而實現了對生產線的實時監控，並且可以通過界面設置系統的一些參數，同時提供了較強大的報警功能。
  2. In addition, a novel heuristic approach which we called “ improved simulated annealing algorithm ” is proposed for bounding maximum and minimum leakage power. 2. a design method for low power clock network is proposed

    通過對高性能通用處理器中時序邏輯特點的詳細分析，提出採用帶門控使能的多比特觸發器設計方法來降低時鐘功耗。
  3. A novel quantum neural computational model is constructed based on the universal quantum gates unit ( i. e. phase - shift gate and controlled not gate ), which acts as the basic computational component

    研究以通用量子邏輯門組（即相移門和受控非門）作為計算基函數，構造新的量子神經計算網路模型。
  4. Thirdly, the paper researchs the application of single electron transistor and the synthesis theory of cicuit based on quantum dot cellular automata by synthesis example of quantum cellular neural network based on build schr ? dinger equation of coupling quantum dot. at last, the paper researchs digital integrated circuit design based on quantum dot cellular automata and design a 8 - bit quantum dot cellular adder by qcadsign based on a method of majority logic reducetion for quantum cellular automata, it prove this designer of 8 - bit quantum dot cellular adder is correctly

    Dinger ）方程為基礎的量子點細胞自動機電路綜合理論，本文以量子細胞神經網路為綜合實例，建立耦合量子點的薛定鄂（ schr ? dinger ）方程組，通過化簡得到類似細胞神經網路的非線性電路方程。最後研究了基於量子點細胞自動機數字集成電路設計，通過建立邏輯方程，簡化邏輯方程，並設計基於精簡qca擇多邏輯門8位加法器，並用qcadesign進行了模擬，實驗證明設計正確性。
  5. Universal logic gate

    通用邏輯門
  6. The quantum gate array is the natural quantum generalization of acyclic combinational logic " circuit " studied in conventional computational complexity theory. in 1995, barenco showed that almost any two - bit gate is universal, so building a feasible two - bit logic gate is the first step to engineer a quantum computer. in principle, the quantum bit can be carried by any two states system

    在眾多的量子計算機模型中目前討論最廣泛的是量子計算機門組網路模型，量子計算機門組網路模型是經典計算機門組網路結構的量子推廣，它是根基於barenco等人所證明的「一個兩比特受控操作和對單比特進行任意操作的門可以構成一個『通用量子邏輯門組』 」之上的。
  7. This paper presents the conversion from dynamic logic gate to markov chain, the solution of dynamic subtree top event failure probability and the method of obtaining the failure mode of subsystem using markov model, that is sequence cutsets of the dynamic subtree. the typical approach to importance analysis of component is impractical for large systems in markov model, so this paper also provides a simple and intuitionistic graph solution based on markov chain

    論文研究了動態邏輯門向馬爾可夫鏈的轉化方法，利用馬爾可夫鏈法求解動態子樹頂事件概率，以及通過馬爾可夫狀態轉移圖直接找齣子系統的故障模式和薄弱環節，即得到動態子樹的順序割集。
  8. Through analyzing the present chengdu electronic government network with the economical and practical thought, the paper propose a solution that selects domestic nc ( network computer ), domestic servers, and domestic linux os to build up a economical and adequate foundation information platform ; that uses open source java tools to develop essential and effective electronic government cooperation office software corresponding with our national conditions, addressing the demand of daily archives transfer, information communication and conference management ; that develops the data exchange engine based on xml and mail to apply safe data exchange between the office software in the electronic government network and the government portal in the internet, according to the logic separation of the electronic government network and internet

    本論文本著經濟實用的思想，利用成都市現有的電子政務網路進行合理劃分、設計，合理選型國產nc網路計算機（ networkcomputer ） 、國產linux操作系統來搭建經濟、夠用的基礎信息平臺：利用開源的java工具開發適合中國國情簡潔、有效的電子政務協同辦公軟體，可滿足政府日常公文流轉、信息溝通、會議管理等需求：根據電子政務外網與公網邏輯隔離的特點，開發基於xml和郵件的數據交換引擎實現電子政務外網中辦公軟體和公眾網中政府門戶網站的安全數據交換。
  9. A distinguishable faults test generation method for digital circuits is presented. the features of basic gate circuits and neural networks are used to establish the test model, and to generate the test patterns for given faults. the fault model and constrained circuit are studied. some strategies, e. g, the reduction of the size of neural network, are proposed in order to accelerate test generation process. the experimental results demonstrate that the algorithm proposed in the paper is effective

    研究一種基於人工神經網路的能區分故障的數字電路測試生成方法，該方法利用電路基本邏輯門的特性和神經網路模型的特點，首先建立測試生成的神經網路模型，然後通過求解網路能量函數的最小值點獲得給定類型故障的測試矢量，其研究結果在可區分故障的測試生成方面提供了一種可能的新途徑
  10. With the fast development of the field programmable gate arrays ( fpga ), the pci ipcore has been offered by a great many manufactories, and then the engineers can integrate the users ’ logic and pci ipcore into the fpga chip, thus the simulations and the verifications of the user ’ logic can be done in the top level. so the engineers can develop pci productions with using ipcore much faster than using special chip of pci interface, and also can shorten debug periods, highly advance the integration of the pcb board

    隨著fpga （現場可編程門陣列）技術的快速發展，很多製造廠商都開始提供pci介面核邏輯（ ipcore ） ，設計者可以將pci用戶邏輯和pci核邏輯集成到fpga裏面，並且可以在頂層通過模擬來驗證pci介面以及用戶邏輯設計的正確與否，這樣較之使用那些pci專用介面晶元，使用ipcore就可以大幅度的提高調試速度，縮短開發周期，提高電路板的集成度和系統的性能。
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