邏輯加法器 的英文怎麼說

中文拼音 [luójiāfǎqì]
邏輯加法器 英文
logical adder
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 邏輯 : logic
  • 法器 : [宗教] musical instruments used in a buddhist or taoist mass
  1. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  2. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  3. Checksum cannot validate tables with column filters, or logical table structures where column offsets differ due to alter table statements that drop or add columns. data in

    校驗和無法驗證帶有列篩選器的表或列偏移量不一致的邏輯表結構（由於存在用於刪除或添加列的alter table語句） 。
  4. The checksum routines released in sql server version 7. 0 cannot validate tables with column filters, or logical table structures where column offsets differ due to alter table statements that drop or add columns

    在sql server 7 . 0版中發布的校驗和常式無法驗證帶有列篩選器的表或列偏移量不一致的邏輯表結構（由於存在用於刪除或添加列的alter table語句） 。
  5. Thirdly, the paper researchs the application of single electron transistor and the synthesis theory of cicuit based on quantum dot cellular automata by synthesis example of quantum cellular neural network based on build schr ? dinger equation of coupling quantum dot. at last, the paper researchs digital integrated circuit design based on quantum dot cellular automata and design a 8 - bit quantum dot cellular adder by qcadsign based on a method of majority logic reducetion for quantum cellular automata, it prove this designer of 8 - bit quantum dot cellular adder is correctly

    Dinger ）方程為基礎的量子點細胞自動機電路綜合理論，本文以量子細胞神經網路為綜合實例，建立耦合量子點的薛定鄂（ schr ? dinger ）方程組，通過化簡得到類似細胞神經網路的非線性電路方程。最後研究了基於量子點細胞自動機數字集成電路設計，通過建立邏輯方程，簡化邏輯方程，並設計基於精簡qca擇多邏輯門8位加法器，並用qcadesign進行了模擬，實驗證明設計正確性。
  6. Dbf algorithms for 2d planar array based on the algorithms for 1d array are discussed in this paper. the author ' s main contributions include research of the adaptive digital beamforming algorithm, which control both amplitude and phase of each array element : diagonal loading qrd - smi algorithm. research of two phase - only dbf algorithms : small phase perturbation restriction algorithm and maximum gain of the expected direction restriction algorithm

    面陣的數字波束形成演算法是面陣dbf技術的關鍵，本文在現有的一維數字波束形成演算法基礎上，研究了二維面陣的數字波束形成演算法，主要工作有：面陣的幅度相位全控制自適應數字波束形成演算法? ?對角加載qrd - smi演算法的研究；兩種面陣唯相位（ phase - only ）數字波束形成演算法? ?小相位擾動約束演算法和期望方向增益最大約束演算法的研究；面陣的數字多波束形成演算法? ?二維fft多波束的研究，以及fft在可編程邏輯器件中的實現。
  7. The primary contents and innovations of this article are introduced below. in order to take advantage of the high speed of calculation, and at the same time, improve the accuracy and dynamic - range of the algorithm, three kinds of multi - input floating point adder algorithm ( fpa ) are summarized and a high - performance multi - input fpa structure is put forward with a self - defined floating point format. the performance of the high - performance structure on calculation speed and logic resource consuming is better than the normal structure

    論文的主要工作及創新點如下:為了充分利用fpga處理速度快的特點，同時盡量提高演算法的精度及動態范圍，本文在對浮點加法器演算法進行深入研究的基礎上，規納總結了三種不同的多輸入浮點加法器演算法，並創造性地提出了一種高效的多輸入浮點加法器結構及一種適合於fpga實現的自定義浮點數格式，這種高效的結構在所需的邏輯資源和運算速度上均遠優于傳統的多輸入結構。
  8. Aimed at performance improvement for the iocp multimedia network server in large - scale complex environment, this paper presents the methods concerned with network base development, configuration design and the logical module design as follows : elevate data processing efficiency by optimizing the data package and transmission, enhance code reusability and extendibility by modular construction, and further optimize the logical module performance through port dispatch

    摘要面臨iocp多媒體網路服務器所的大復雜度環境設計問題，本文論述該網路服務器的網路底層開發、結構設計及邏輯模塊設計，提出提高其性能的方法：優化數據封裝以及投遞方式，增加數據的處理效率；整體結構模塊化設計，提高代碼的可重用性以及可擴展性；通過埠分流的方式，實現對邏輯模塊性能改進。
  9. The vd is composed of four functional units : 1 ) the branch metrics unit ( bmu ) ; 2 ) the add - compare - select unit ( acs ) ; 3 ) the path metrics unit ( pmu ) ; 4 ) the survivor memory unit ( smu ) ; regarding the power dissipation of the viterbi decoder, the smu is the hottest spot in the viterbi decoder due to the frequent memory accesses. there are two traditional techniques for the realization of survivor memory unit in viterbi decoder - - register exchange ( re ) and trace back ( tb ) method

    這是當前開展低功耗邏輯優化的重要方面，也是本課題採用的方法。 viterbi譯碼器主要由四個功能單元組成:分支度量單元（ bmu ） ，加比選單元（ acs ） ，路徑度量存儲單元（ pmu ） ，倖存路徑存儲和輸出單元（ smu ） 。本文所做的viterbi譯碼器設計採用模塊化的設計方法，先對各個功能單元進行優化設計，然後將各個功能單元組合在一起，形成最終的譯碼器。
  10. You can also add client - side validation to check user input before the page is submitted by writing a function in ecmascript javascript that duplicates the logic of the server - side method

    您還可以通過編寫ecmascript （ javascript ）函數，重復服務器端方法的邏輯，從而添加客戶端驗證，在提交頁面之前檢查用戶輸入內容。
  11. 2. with a view to the theory of dds, this paper introduces the realization of dds, which based on programmable device. it also discusses in detail some key techniques such as the design of high speed phase accumulator and ram

    2 .從dds的原理出發，著重介紹了一種自行設計的基於可編程邏輯器件fpga的dds電路的實現方法，並對其高速相位累加器、 ram查找表等關鍵技術進行了詳細討論。
  12. Finally, the effect of the diffraction aperture is studied during the course of reducing the scale of the diffraction aperture to the limit of the scalar diffraction theory

    基於仙農（ shanon ）的組合邏輯設計理論，用光學矢量-矩陣乘法器對超前進位加法器模型的光學實現進行了數值模擬。
  13. To achieve tuning the gain of the controller by software and digital logical circuits, this article took the first method for example and introduced the tuning process and tuning result in detail, meanwhile, it has also been validated by the experiments and matlab

    一種是通過計算機軟體對控制器增益進行調節，另?種是運用數字邏輯電路來調節增益，以第一種方法為例，詳細的介紹了調節過程、調節結果，並用實驗和計算機模擬加以驗證。
  14. Add into the fold the ability for hardware servers to create both static and dynamic partitions i ll call them logical partitions, or lpars, in this article, but different hardware vendors call these different things, and you re likely to have more questions that need answering

    為硬體服務器增加了創建靜態和動態分區的能力。 （在本文中我將它們稱作邏輯分區，或者lpar ，但是不同的硬體供應商可能有不同的叫法） ，您可能還有更多的問題要問。
分享友人
分享到 Line

分享到臉書