邏輯單元號 的英文怎麼說
中文拼音 [luódānyuánháo]
邏輯單元號
英文
lun logical unit number-
By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument
本文具體給出了新型智能儀器硬體結構及實現,描述了智能儀器硬體設計細節,包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等,詳細地給出了設計原理圖和電路圖;給出了新型智能儀器的軟體設計細節,從而完成了新型智能儀器完整的軟硬體設計。Finally this paper propose the structure diagram of adaptive distance protection based on neural network impedance relay, which describes entire logic procedure from data acquisition unit to trip unit
最後提出基於神經網路阻抗繼電器的自適應距離保護結構框圖,描述從信號採集單元到動作出口單元的整個邏輯過程,並對自適應距離保護的前景作出展望。To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation
論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點,在對目前微機勵磁控制器分析基礎上,提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案,運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元,並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法,通過電路數字模擬對所設計的數字觸發單元進行了驗證。The gates would have to be stacked on top of a template of cmos transistors that would relay signals indicating when each gate element should begin and stop processing
這些邏輯閘得疊在設計好的cmos電晶體板子上,電晶體會給出訊號,告知每個單元閘在什麼時候可以開始或停止處理資訊。The first three numbers for each item refer to scsi bus, device id, and lun logical unit number, respectively
每一項的前三個數字分別指scsi總線、設備標識和lun (邏輯單元號, logical unit number ) 。Mask the logical unit number corresponding to the reporting volume to hide it from the reporting servers
屏蔽與報表卷相對應的邏輯單元號碼( lun ) ,使報表服務器無法識別該號碼。Unmask the logical unit number corresponding to each reporting volume to make the volume accessible to the production server
取消與每個報表卷相對應的邏輯單元號碼( lun )的掩碼,以使生產服務器可以訪問該卷。Using your hardware vendor s utilities, unmask the logical unit number corresponding to each reporting volume to make the volume accessible to the production server
使用硬體供應商的實用工具,公開對應于每個報表卷的邏輯單元號碼( lun )以使生產服務器可訪問到該卷。A design ot portable digital oscillograph based on dsp is presented. a integrated prototype is composed of high speed data processing module by which signal is digitalized, data processing unit whose core is dsp, general controller as which cpld is used and terminal facility - - lcd
通過高速數據採集模塊將信號數字化,以高性能數字信號處理器tms320vc5402為核心構成數據處理單元,採用高密度的可編程邏輯器件epf6016a設計儀器的系統控制單元,使用液晶顯示器做為終端顯示設備,構成一個完整的示波表樣機。Clauses can be grouped to operate as a single unit separate from the rest of the query ; like putting parentheses around an expression in a mathematical equation or logic statement
可以對子句進行分組,使其作為獨立於查詢的其餘部分的一個單元來工作,這類似於在數學等式或邏輯語句中的表達式兩側加上括號。Query clauses can be grouped to operate as a single unit separate from the rest of the query, similar to putting parentheses around an expression in a mathematical equation or logic statement. when you group clauses, the
可以對查詢子句進行分組,使其作為獨立於查詢的其餘部分的一個單元來工作,這類似於在數學等式或邏輯語句中的某個表達式兩側加上括號。The paper analyses its key circuit and software program structure. this full - digital controller is made up of dsp and implements single neuron adaptive pid computation, current pi computation, logical determination, pulse - fire and procession of protective signal etc. it also improves the reliability and availability of this control system
本課題對控制器主要的電路結構及程序結構進行了分析,以dsp為核心組成的全數字式控制器完成了電流pi演算法計算,單神經元自適應pid演算法計算、邏輯判斷、脈沖觸發以及系統保護信號的處理等,提高了控制器的可靠性和可操作性。The clock and data pulsation signals from upper sensor heads can be received using pin diode, then, amplified and inverted in logical control unit for the purpose of cpu operation. hereinafter, the digital signal will be delivered into the central processing unit ( cpu ) for related calculation, and meanwhile transmitted to a d / a converter for signal recovery after filter and phase - shift circuit
通過採用pin管接收從傳感頭傳遞下來的時鐘脈沖和數據脈沖信號,並將它們放大整形傳送到邏輯控制單元,產生邏輯控制信號,再將數字信號傳送給d / a轉換器,設計了濾波器和移相器電路,還原出了原始的被采樣信號。A design of the feeder terminal unit based on dsp is presented. an integrated prototype is composed of a 6 - channel voltage collector, a 6 - channnel current collector, a 16 - channel state collection a 2 - channel impulse collector, a data processing unit whose core is dsp, a general controller in which cpld is used
系統通過6路電流採集、 6路電壓採集、 16路的狀態採集以及2路的脈沖採集獲取相應的數據信息;以高性能數字信號處理器tms320vc5402為核心構成數據處理單元;以高性價比的可編程邏輯器件epm7128為全局控制器;同時數據可以通過鍵盤和數碼管進行現場控制。分享友人